cmpldes2.tcl

design compile synthesis user guide

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# Tcl script file for second part of Chapter 9
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# Note: This script is run after the first compile completes.
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# Remove any designs in memory
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remove_design -all
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# Read in the optimized design
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read_file -format db [list ./db/compile.db]
set current_design {compile.db:TOP}
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# Generate the area and constraints reports
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report_area
report_constraint
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# Set new constraints
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create_clock -name CLK -period 23 -waveform [list 0 11.5] [list CLK]
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# Reoptimize the design and explore the design space
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compile -map_effort medium -verify -verify_effort low -boundary_optimization
set current_design {compile.db:TOP}
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# Generate area and constraints reports on the optimized design
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report_area
report_constraint
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# Save the optimized design
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write -format db -hierarchy -output {./db/TOP_compiled.db} [list {compile.db:TOP}]
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# Delete designs
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remove_design [find design {*}]
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# ****** Optional Exercise - Instance-Specific Hierarchy ******
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read_file -format db [list {./db/TOP_before_compile.db}]
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# set current design to TOP
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set current_design TOP
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# set current instance to CONVERTOR_CKT TOP/U3
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current_instance U3
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# set current instance to CONVERTOR_1 TOP/U3/U7
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current_instance U7
report_net
set_load 2.5 A0
report_net
current_instance .
current_instance ..
current_instance
#
quit