代码搜索：CPLD FPGA

找到约 10,000 项符合「CPLD FPGA」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/371662/9543121

qmsg prev_cmp_davincihd.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
·
www.eeworm.com/read/371662/9543185

qmsg davincihd.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
·
www.eeworm.com/read/364617/9903051

qmsg led.fit.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu
·
www.eeworm.com/read/167918/9947584

vhd top_comp.vhd

library IEEE; use IEEE.STD_LOGIC_1164.all; package top_comp is --------------------------------------------------------------------------------------------------- component sm_module port(
·
www.eeworm.com/read/167055/9982922

mti fulladder.cr.mti

{F:/FPGA exp/FullAdder/top.vhd} {1 {vcom -work work -2002 -explicit {F:/FPGA exp/FullAdder/top.vhd} Model Technology ModelSim SE vcom 6.1b Compiler 2005.09 Sep 8 2005 -- Loading package standard -
·
www.eeworm.com/read/452005/7452210

ucf system.ucf

############################################################################ ## This system.ucf file is generated by Base System Builder based on the ## settings in the selected Xilinx Board Definitio
·
www.eeworm.com/read/448006/7541957

ref hdllib.ref

EN bcd_7seg NULL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg.vhd sub00/vhpl00 EN bcd_7seg_sch NULL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf sub00/vhpl04 EN d3_8e_mxilinx_bcd_7seg_sch NULL G:/vijay_FPGA_L
·
www.eeworm.com/read/447993/7542522

cmd_log bit_add.cmd_log

xst -intstyle ise -ifn __projnav/bit_add.xst -ofn bit_add.syr xst -intstyle ise -ifn __projnav/bit_add.xst -ofn bit_add.syr ngdbuild -intstyle ise -dd g:\vijay_fpga_lab\1bit_add/_ngo -i -p xc3s50-p
·
www.eeworm.com/read/330802/12867960

zsf wed.zsf

F:/fpga test/mcu_sram_test/mcu_sram_test.vwf 0 6151866 777 6151866 2 F:/fpga test/mcu_sram_test/sram_control.vwf 0 1000000 859 1000000 0 F:/fpga test/mcu_sram_test/mcu_fpga_control.vwf 1328000 26560
·
www.eeworm.com/read/327630/13069993

qmsg phase_shift_sin.fit.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
·