led.fit.qmsg

适用于FPGA初学者,一个流水灯的程序,用VERILOG语言写的.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 19 13:15:54 2008 " "Info: Processing started: Fri Sep 19 13:15:54 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off led -c led " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off led -c led" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "led EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"led\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_50mhz (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node clk_50mhz (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0}  } { { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_50mhz" } } } } { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "" { clk_50mhz } "NODE_NAME" } "" } } { "D:/fpga practice/led/led/led.fld" "" { Floorplan "D:/fpga practice/led/led/led.fld" "" "" { clk_50mhz } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.049 ns register register " "Info: Estimated most critical path is register to register delay of 2.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shift_led:shift_led\|led_out\[1\] 1 REG LAB_X54_Y1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X54_Y1; Fanout = 3; REG Node = 'shift_led:shift_led\|led_out\[1\]'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "" { shift_led:shift_led|led_out[1] } "NODE_NAME" } "" } } { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 40 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.447 ns) 0.819 ns shift_led:shift_led\|reduce_nor~125 2 COMB LAB_X53_Y1 1 " "Info: 2: + IC(0.372 ns) + CELL(0.447 ns) = 0.819 ns; Loc. = LAB_X53_Y1; Fanout = 1; COMB Node = 'shift_led:shift_led\|reduce_nor~125'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "0.819 ns" { shift_led:shift_led|led_out[1] shift_led:shift_led|reduce_nor~125 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.125 ns) + CELL(0.447 ns) 1.391 ns shift_led:shift_led\|reduce_nor~129 3 COMB LAB_X53_Y1 1 " "Info: 3: + IC(0.125 ns) + CELL(0.447 ns) = 1.391 ns; Loc. = LAB_X53_Y1; Fanout = 1; COMB Node = 'shift_led:shift_led\|reduce_nor~129'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "0.572 ns" { shift_led:shift_led|reduce_nor~125 shift_led:shift_led|reduce_nor~129 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.144 ns) + CELL(0.428 ns) 1.963 ns shift_led:shift_led\|reduce_nor~0 4 COMB LAB_X53_Y1 1 " "Info: 4: + IC(0.144 ns) + CELL(0.428 ns) = 1.963 ns; Loc. = LAB_X53_Y1; Fanout = 1; COMB Node = 'shift_led:shift_led\|reduce_nor~0'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "0.572 ns" { shift_led:shift_led|reduce_nor~129 shift_led:shift_led|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.049 ns shift_led:shift_led\|led_out\[0\] 5 REG LAB_X53_Y1 3 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 2.049 ns; Loc. = LAB_X53_Y1; Fanout = 3; REG Node = 'shift_led:shift_led\|led_out\[0\]'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "0.086 ns" { shift_led:shift_led|reduce_nor~0 shift_led:shift_led|led_out[0] } "NODE_NAME" } "" } } { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.408 ns 68.72 % " "Info: Total cell delay = 1.408 ns ( 68.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.641 ns 31.28 % " "Info: Total interconnect delay = 0.641 ns ( 31.28 % )" {  } {  } 0}  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "2.049 ns" { shift_led:shift_led|led_out[1] shift_led:shift_led|reduce_nor~125 shift_led:shift_led|reduce_nor~129 shift_led:shift_led|reduce_nor~0 shift_led:shift_led|led_out[0] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Warning" "WDAT_PRELIMINARY_TIMING" "EP2C35F672C6 " "Warning: Timing characteristics of device EP2C35F672C6 are preliminary" {  } {  } 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "18 " "Warning: Found 18 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[0\] 0 " "Warning: Pin \"led_out\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[1\] 0 " "Warning: Pin \"led_out\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[2\] 0 " "Warning: Pin \"led_out\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[3\] 0 " "Warning: Pin \"led_out\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[4\] 0 " "Warning: Pin \"led_out\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[5\] 0 " "Warning: Pin \"led_out\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[6\] 0 " "Warning: Pin \"led_out\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[7\] 0 " "Warning: Pin \"led_out\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[8\] 0 " "Warning: Pin \"led_out\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[9\] 0 " "Warning: Pin \"led_out\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[10\] 0 " "Warning: Pin \"led_out\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[11\] 0 " "Warning: Pin \"led_out\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[12\] 0 " "Warning: Pin \"led_out\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[13\] 0 " "Warning: Pin \"led_out\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[14\] 0 " "Warning: Pin \"led_out\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[15\] 0 " "Warning: Pin \"led_out\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[16\] 0 " "Warning: Pin \"led_out\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_out\[17\] 0 " "Warning: Pin \"led_out\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0}  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 20 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 19 13:16:05 2008 " "Info: Processing ended: Fri Sep 19 13:16:05 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0}  } {  } 0}