fulladder.cr.mti

来自「四位全家器的VHDL语言模块」· MTI 代码 · 共 11 行

{F:/FPGA exp/FullAdder/top.vhd} {1 {vcom -work work -2002 -explicit {F:/FPGA exp/FullAdder/top.vhd}
Model Technology ModelSim SE vcom 6.1b Compiler 2005.09 Sep  8 2005
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling entity full_adder
-- Compiling architecture behavioral of full_adder

} {} {}}