top_comp.vhd

FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package top_comp is

---------------------------------------------------------------------------------------------------
component	sm_module
port(
		gclk_in				:	in	std_logic;
		clk_rx_in			:	in	std_logic;		
		rx_offset			:	in	std_logic_vector(18 downto 0);
		sm_out				:	out	std_logic_vector(18 downto 0);
		sm_offset_out	:	out	std_logic_vector(18 downto 0));		
end component;
---------------------------------------------------------------------------------------------------
component	rf3030_module
port(					
		gclk_b_N_in	:	in	std_logic;			--61.44MHz clock signal from rf3030
		gclk_b_P_in	:	in	std_logic;					
		gclk_b_out	:	out	std_logic;	
		IQ_sel_rf3030_N_in	:	in	std_logic;
		IQ_sel_rf3030_P_in	:	in	std_logic;
		IQ_sel_3030_N_nouse	:	in		std_logic;
		IQ_sel_3030_P_nouse	:	in		std_logic;
		Rf3030_aux_N		:	in	std_logic_vector(4 downto 0);							
		Rf3030_aux_P		:	in	std_logic_vector(4 downto 0);
		Rf3030_marker_N	:	in	std_logic_vector(4 downto 1);
		Rf3030_marker_P	:	in	std_logic_vector(4 downto 1);						
		data_from_rf3030_N_in	:	in	std_logic_vector(15 downto 0);	--code rate 61.44MHz,I、Q crossed	
		data_from_rf3030_P_in	:	in	std_logic_vector(15 downto 0);
		data_rx_I	:	out	std_logic_vector(15 downto 0);	   			
		data_rx_Q	:	out	std_logic_vector(15 downto 0);
		test			:	out	std_logic);
end component;
---------------------------------------------------------------------------------------------------
component	dsp_ram_module
port(
		dsp_fpga_data	:	inout	std_logic_vector(31 downto 0);
		dsp_fpga_addr	:	in		std_logic_vector(20 downto 3);
		dsp_fpga_clk	:	in		std_logic;	
		dsp_fpga_we	:	in	std_logic;
		dsp_fpga_oe	:	in	std_logic;
		dsp_fpga_ce1	:	in	std_logic;		
		dsp_fpga_ext_int4	:	out std_logic;
		dsp_fpga_ext_int5	:	out std_logic;		
		dsp_fpga_ext_int6	:	out std_logic;
		dsp_fpga_ext_int7	:	out std_logic;
		gclk_o		:	in	std_logic;
		clk_rx		:	in	std_logic;
		addr_tx		:	in	std_logic_vector(12 downto 0);	
		addr_rx		:	in	std_logic_vector(12 downto 0);
		rx_offset_out			:	out	std_logic_vector(12 downto 0);
		dsp_ram_rx_dina		:	in	std_logic_vector(31 downto 0);	 	--ram_rx A port input data bus					
		dsp_ram_tx_douta	: out	std_logic_vector(31 downto 0));	
end component;
---------------------------------------------------------------------------------------------------
component rf3020_module
port (
			gclk_in		:	in	std_logic;
			sm				:	in	std_logic_vector(2 downto 0);
			din_I			:	in	std_logic_vector(15 downto 0);
			din_Q			: in std_logic_vector(15 downto 0);
			dout_p    : out std_logic_vector(15 downto 0);
			dout_n    : out std_logic_vector(15 downto 0);
			clk_8x_p 	: out std_logic;
			clk_8x_n 	: out std_logic;
			sel_iq_p  : out std_logic;
			sel_iq_n  : out std_logic;
			aux_N			:	out	std_logic_vector(4 downto 0);
			aux_P			:	out	std_logic_vector(4 downto 0);
			marker_N	:	out	std_logic_vector(4 downto 1);
			marker_P	:	out	std_logic_vector(4 downto 1));
end component;
---------------------------------------------------------------------------------------------------
end top_comp;