代码搜索：ADPLL
找到约 28 项符合「ADPLL」的源代码
代码结果 28
www.eeworm.com/read/334090/12640924
s startup.s
;=====================================================================
; company: COMMIT Incorporated
; department: HW
www.eeworm.com/read/374925/6293439
pdf a high-speed variable phase accumulator for an adpll architecture.pdf
www.eeworm.com/read/334090/12641196
h crpm.h
//*********************************************************************\\
// company: COMMIT Incorporated \\
// department: HW
www.eeworm.com/read/435698/7786607
txt xiangweiji.txt
相位测量仪的分模块原理框图(以分辨率为0.1°为例)如图3-2所示。基准信号(相位基准)Fr经放大整形后加到锁相环的输入端，在锁相环的反馈环路中设置一个N=3600的分频器，使锁相环的输出信号频率为3600Fr，但相位与Fr相同，这个输出信号被用作计数器的计数时钟。被测信号Fs经整形放大再2分频后得到的Fs／2与Fr／2送入由异或门组成的相位比较电路，其输出脉冲A的脉宽Tp反映了两列信号的相位差。 ...
www.eeworm.com/read/245509/12796710
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity tb_ADPLL is
generic(
del : integer := 1;
cnt_size : integer := 4;
cycle_time : integer := 200
www.eeworm.com/read/173473/9655909
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity tb_ADPLL is
generic(
del : integer := 1;
cnt_size : integer := 4;
cycle_time : integer := 200
www.eeworm.com/read/245509/12796702
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ADPLL is
generic(
cnt_size : integer := 4;
del : integer := 1;
duty : integer := 2;
www.eeworm.com/read/173473/9655905
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ADPLL is
generic(
cnt_size : integer := 4;
del : integer := 1;
duty : integer := 2;