_primary.vhd

来自「verilog ADPLL file with testbench.v」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity tb_ADPLL is
    generic(
        del             : integer := 1;
        cnt_size        : integer := 4;
        cycle_time      : integer := 200
    );
end tb_ADPLL;