crpm.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//*********************************************************************\\
//        company:               COMMIT Incorporated                   \\
//        department:            HW                                    \\
//        author:                LiYuan                                \\
//        version:               1.0                                   \\
//        create date:           09/20/2005                            \\
//        release date:                                                \\
//        final revise date:                                           \\
//        reviser:                                                     \\
//        file descript:                                               \\
//*********************************************************************\\

//#define _DPLL_SWIMode

//registers define
static unsigned int ULPDR_Base_Addr = 0xfffb1000;
#define  ULPDR_COUNTER_32_LSB_REG               *(volatile unsigned short *)(ULPDR_Base_Addr + 0x00)
#define  ULPDR_COUNTER_32_MSB_REG               *(volatile unsigned short *)(ULPDR_Base_Addr + 0x02)
#define  ULPDR_COUNTER_HIGH_FREQ_LSB_REG        *(volatile unsigned short *)(ULPDR_Base_Addr + 0x04)
#define  ULPDR_COUNTER_HIGH_FREQ_MSB_REG        *(volatile unsigned short *)(ULPDR_Base_Addr + 0x06)
#define  ULPDR_GAUGING_CTRL_REG                 *(volatile unsigned short *)(ULPDR_Base_Addr + 0x08)
#define  ULPDR_IT_STATUS_REG                    *(volatile unsigned short *)(ULPDR_Base_Addr + 0x0a)
#define  ULPDR_SETUP_ULPD1_CELL2_REG            *(volatile unsigned short *)(ULPDR_Base_Addr + 0x14)
#define  ULPDR_SETUP_ULPD1_CELL3_REG            *(volatile unsigned short *)(ULPDR_Base_Addr + 0x12)
#define  ULPDR_SETUP_ULPD1_CELL4_REG            *(volatile unsigned short *)(ULPDR_Base_Addr + 0x2e)
#define  ULPDR_SOFT_REQ_REG                     *(volatile unsigned short *)(ULPDR_Base_Addr + 0x1a)
#define  ULPDR_STATUS_REQ_REG                   *(volatile unsigned short *)(ULPDR_Base_Addr + 0x20)
#define  ULPDR_SLEEP_STATUS_REG                 *(volatile unsigned short *)(ULPDR_Base_Addr + 0x2c)
#define  ULPDR_APLL_CTRL_REG                    *(volatile unsigned short *)(ULPDR_Base_Addr + 0x26)
#define  ULPDR_PWR_CTRL_REG                     *(volatile unsigned short *)(ULPDR_Base_Addr + 0x28)
#define  ULPDR_SOFT_DISABLE_REQ_REG             *(volatile unsigned short *)(ULPDR_Base_Addr + 0x34)
#define  ULPDR_RESET_STATUS_REG                 *(volatile unsigned short *)(ULPDR_Base_Addr + 0x36)
#define  ULPDR_REVISION_NUMBER_REG              *(volatile unsigned short *)(ULPDR_Base_Addr + 0x38)
#define  ULPDR_CLK_IO_CTRL_REG                  *(volatile unsigned short *)(ULPDR_Base_Addr + 0x3a)
#define  ULPDR_ENA_MEMORY_RETENTION_REG         *(volatile unsigned short *)(ULPDR_Base_Addr + 0x42)
#define  ULPDR_INC_FRAC_REG                     *(volatile unsigned short *)(ULPDR_Base_Addr + 0x80)
#define  ULPDR_INC_SIXTEENTH_REG                *(volatile unsigned short *)(ULPDR_Base_Addr + 0x82)
#define  ULPDR_SETUP_FRAME_REG                  *(volatile unsigned short *)(ULPDR_Base_Addr + 0x84)
#define  ULPDR_GSM_TIMER_INIT_REG               *(volatile unsigned short *)(ULPDR_Base_Addr + 0x86)
#define  ULPDR_GSM_TIMER_IT_STATUS_REG          *(volatile unsigned short *)(ULPDR_Base_Addr + 0x88)
#define  ULPDR_GSM_TIMER_VALUE_REG              *(volatile unsigned short *)(ULPDR_Base_Addr + 0x8a)
#define  ULPDR_GSM_TIMER_CTRL_REG               *(volatile unsigned short *)(ULPDR_Base_Addr + 0x8c)
#define  ULPDR_CLOCK_GSM_REG                    *(volatile unsigned short *)(ULPDR_Base_Addr + 0x8e)
#define  ULPDR_CLOCK_26M_CTRL_REG               *(volatile unsigned short *)(ULPDR_Base_Addr + 0x90)

static unsigned int CLKM13_Base_Addr = 0xfffece00;
#define  CLKM13_ARM_CKCTL_REG                   *(volatile unsigned long *)(CLKM13_Base_Addr + 0x00)
#define  CLKM13_ARM_IDLECT1_REG                 *(volatile unsigned long *)(CLKM13_Base_Addr + 0x04)
#define  CLKM13_ARM_IDLECT2_REG                 *(volatile unsigned long *)(CLKM13_Base_Addr + 0x08)
#define  CLKM13_ARM_EWUPCT_REG                  *(volatile unsigned long *)(CLKM13_Base_Addr + 0x0c)
#define  CLKM13_ARM_RSTCT1_REG                  *(volatile unsigned long *)(CLKM13_Base_Addr + 0x10)
#define  CLKM13_ARM_RSTCT2_REG                  *(volatile unsigned long *)(CLKM13_Base_Addr + 0x14)
#define  CLKM13_ARM_SYSST_REG                   *(volatile unsigned long *)(CLKM13_Base_Addr + 0x18)
#define  CLKM13_ARM_CKOUT1_REG                  *(volatile unsigned long *)(CLKM13_Base_Addr + 0x1c)
#define  CLKM13_ARM_IDLECT3_REG                 *(volatile unsigned long *)(CLKM13_Base_Addr + 0x24)
#define  CLKM13_ARM_RETCTL_REG                  *(volatile unsigned long *)(CLKM13_Base_Addr + 0x28)

static unsigned int CLKM2_Base_Addr = 0xe1008000;
#define  CLKM2_DSP_CKCTL_REG                   *(volatile unsigned short *)(CLKM2_Base_Addr + 0x00)
#define  CLKM2_DSP_IDLECT1_REG                 *(volatile unsigned short *)(CLKM2_Base_Addr + 0x04)
#define  CLKM2_DSP_IDLECT2_REG                 *(volatile unsigned short *)(CLKM2_Base_Addr + 0x08)
#define  CLKM2_DSP_RSTCT2_REG                  *(volatile unsigned short *)(CLKM2_Base_Addr + 0x14)
#define  CLKM2_DSP_SYSST_REG                   *(volatile unsigned short *)(CLKM2_Base_Addr + 0x18)

static unsigned int ADPLL1_Base_Addr = 0xfffecf00;
#define  ADPLL1_REG0_REG                        *(volatile unsigned short *)(ADPLL1_Base_Addr + 0x00)
#define  ADPLL1_REG1_REG                        *(volatile unsigned short *)(ADPLL1_Base_Addr + 0x02)
#define  ADPLL1_REG2_REG                        *(volatile unsigned short *)(ADPLL1_Base_Addr + 0x04)
#define  ADPLL1_REG3_REG                        *(volatile unsigned short *)(ADPLL1_Base_Addr + 0x06)


typedef enum
{	
soft_IO                = 12, 
soft_uWire             = 11,
soft_MMC2              = 9,
soft_MMC               = 8,
soft_UART3             = 7,
soft_UART2             = 6,
soft_UART1             = 5,                             
soft_USBOTG            = 4,
soft_USBPVCI           = 3,
soft_MCSI              = 2,
soft_CAMERA            = 1,                
soft_APLL              = 0                             
} soft_dev_t;

//fuctions declaration
void DPLL_Setup(int);
void SoftOpen_Dev(soft_dev_t);
void SoftClose_Dev(soft_dev_t);
void CRPMRegResetValueTest(void);