startup.s

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

;=====================================================================
;        company:               COMMIT Incorporated                   
;        department:            HW                                    
;        author:                HW                                    
;        version:               1.0                                   
;        create date:           11/22/2005                            
;        release date:                                                
;        final revise date:                                           
;        reviser:                                                     
;        file descript:                                               
;=====================================================================


	.state32
	.sect ".intvecs"
    
	.global _reset
	.global _c_int00
	.global _EX_AbortD
	.global _EX_AbortP
	.global _EX_IRQ
	.global _EX_FIQ
	.global INT_SWI

	.global $DPLL_SWI
    .global cinit
	.ref _Initial_MMU

; assembly entry 
_reset:
    LDR	pc, initializationCall
; interrupt service
int_undef: B int_undef          ; undefined interrupt
    LDR pc, INT_SWICall         ; software interrupt
    LDR pc, _EX_AbortPCall      ; abort (prefetch) interrupt
    LDR pc, _EX_AbortDCall      ; abort (data) interrupt
int_reserved: B int_reserved    ; reserved interrupt
    LDR pc, _EX_IRQCall         ; IRQ interrupt
    LDR pc, _EX_FIQCall         ; FIQ interrupt

initializationCall	.word initialization
INT_SWICall  .word  INT_SWI
_EX_AbortDCall  .word  _EX_AbortD
_EX_AbortPCall  .word  _EX_AbortP
_EX_IRQCall  .word  _EX_IRQ
_EX_FIQCall  .word  _EX_FIQ


    .sect ".boot"

; Initialization
initialization:
	; Initialize the
    ; Write Buffer - Disabled    
    ; Caches - Disabled
    ; MMU - Disabled
    ; Endianess - Little
    ; vector location - 0x00000000
    ; alignment fault checking - Disabled
    ;-------------------------
    MOV R0,  #0x0070
    MCR P15, #0, R0, C1, C0, #0
    
    ; Flush both the I and D caches. If the MMU were in use (by a bootloader
    ; or some other OS/application) this will get rid of any of the pages.
    ; Note that with the MMU off, the I cache will cache physical addresses.
    ;-------------------------
    MOV R0,  #0
    MCR P15, #0, R0, C7, C7, #0

    ; Also flush the TLB to ensure that any old translations in the cache
    ; are discarded before re-enabling the MMU.
    ;-------------------------
    MOV R0,  #0
    MCR P15, #0, R0, C8, C7, #0

    ; Enable Instruction cache
    ;-------------------------
    MRC p15, #0, R0, C1, C0, #0
    ORR R0, R0, #0x1000          ; just enable I cache , no Data cache
    ORR R0, R0, #0x0004           ; Enable Instruction cache and Data cache by chenwei
    MCR P15, #0, R0, C1, C0, #0

; Enable ARMPERCK and ARMXORCK
clk_enable:
	LDR r0, CLKM13_ARM_IDLECT2_REG_Addr
	LDR r1, CLKM13_ARM_IDLECT2_REG_Val
	LDR r2, [r0]
	ORR r2, r2, r1
	STR r2, [r0]

	B rst_release

CLKM13_ARM_IDLECT2_REG_Addr  .word  0xFFFECE08
CLKM13_ARM_IDLECT2_REG_Val   .word  0x00000006


; Release ARMPERRST
rst_release:
	LDR r0, CLKM13_ARM_RSTCT2_REG_Addr
	LDR r2, [r0]
	ORR r2, r2, r1
	STR r2, [r0]

	B wd_disable

CLKM13_ARM_RSTCT2_REG_Addr  .word  0xFFFECE14
CLKM13_ARM_RSTCT2_REG_Val   .word  0x00000001


wd_disable:
; Disable MPU WatchDog
    LDR r0, WDTIMER_MPU_TIMER_MODE_REG_Addr
    LDR r1, WDTIMER_MPU_TIMER_MODE_REG_Val_1ST
    LDR r2, WDTIMER_MPU_TIMER_MODE_REG_Val_2ND
    STR r1, [r0]
    STR r2, [r0]

; Disable 32kHz WatchDog
    LDR r0, WDTIMER_WSPR_REG_Addr
	LDR r1, WDTIMER_WWPS_REG_Addr
	LDR	r2, WDTIMER_WSPR_REG_Val_1ST
	LDR	r3, WDTIMER_WSPR_REG_Val_2ND

	STR r2, [r0]
wd_loop1
    LDR r4, [r1]
	TST r4, #0x10
	BNE wd_loop1

	STR r3, [r0]
wd_loop2
    LDR r4, [r1]
	TST r4, #0x10
	BNE wd_loop2
	
	B  interrupt_enable

; WatchDog register define
WDTIMER_MPU_TIMER_MODE_REG_Addr     .word  0xFFFEC808
WDTIMER_MPU_TIMER_MODE_REG_Val_1ST  .word  0x000000F5
WDTIMER_MPU_TIMER_MODE_REG_Val_2ND  .word  0x000000A0

WDTIMER_WSPR_REG_Addr     .word  0xFFFEB048
WDTIMER_WWPS_REG_Addr     .word  0xFFFEB034
WDTIMER_WSPR_REG_Val_1ST  .word  0x0000AAAA
WDTIMER_WSPR_REG_Val_2ND  .word  0x00005555


interrupt_enable:
; Enables a new FIQ and IRQ generation
    LDR r0, INTH_L1_CONTROL_REG_Addr
	LDR r1, INTH_L1_CONTROL_REG_Val
	STR r1, [r0]

	LDR r0, INTH_L2_CONTROL_REG_Addr
	LDR r1, INTH_L2_CONTROL_REG_Val
	STR r1, [r0]

;	B setup_stack
    B mmu_arm ;zhy add for mmu 

; interrupt register difine
INTH_L1_CONTROL_REG_Addr  .word  0xFFFECB18
INTH_L1_CONTROL_REG_Val   .word  0x00000003
INTH_L2_CONTROL_REG_Addr  .word  0xFFFE0018
INTH_L2_CONTROL_REG_Val   .word  0x00000003


;ARM MMU
mmu_arm:
    BL  _Initial_MMU
    LDR r0, MMU_ARM_TTB_BASE_Addr
	MCR p15, #0, r0, c2, c0, #0    ; write TTB base address
	MRC p15,#0,r1,c2,c0,#0   ; For test C2
	MOV  R0, #0xff00
    ADD  R0, R0,#0xFf
;	MOV r0, #ffff
	MCR p15, #0, r0, c3, c0, #0    ; write domain access control
	MRC p15,#0,r1,c3,c0,#0   ; For test C3
;enable MMU
	MRC p15, #0, r0, c1, c0, #0
	ORR r0, r0, #1
	MCR p15, #0, r0, c1, c0, #0

    B setup_stack
MMU_ARM_TTB_BASE_Addr  .word  0x10110000
mmu_arm_ttb  .usect  ".mmu_arm_ttb", 0x00E00000, 16*1024
;MMU_ARM_TTB_BASE_Addr  .word  mmu_arm_ttb




addr_v_int     .word  0x00000000
addr_p_int     .word  0x10000000
len_int        .word  1
desc_int       .word  0x00000c0e

addr_v_cs      .word  0x00100000
addr_p_cs      .word  0x00100000
len_cs         .word  255
desc_cs        .word  0x00000c02

addr_v_sdram   .word  0x10000000
addr_p_sdram   .word  0x10000000
len_sdram      .word  256
desc_sdram     .word  0x00000c0e

addr_v_others  .word  0x20000000
addr_p_others  .word  0x20000000
len_others     .word  256*14
desc_others    .word  0x00000c02

; setup stack	
setup_stack:
	
	MOV	r4, #FIQ_MODE | IRQ_MASK | FIQ_MASK
	MSR	CPSR, r4
	LDR	sp, FIQStackAddr
	ADD	sp, sp, #STACKSIZE

	MOV	r4, #IRQ_MODE | IRQ_MASK | FIQ_MASK
	MSR	CPSR, r4
	LDR	sp, IRQStackAddr
	ADD	sp, sp, #STACKSIZE

	MOV	r4, #ABORT_MODE | IRQ_MASK | FIQ_MASK
	MSR	CPSR, r4
	LDR	sp, abtStackAddr
	ADD	sp, sp, #STACKSIZE

	MOV	r4, #SUP_MODE
	MSR	CPSR, r4
	LDR	sp, svcStackAddr
	ADD	sp, sp, #STACKSIZE

		;initialize the cinit section:
;R4 is the base address of variable table
	LDR	R0,	c_cinit
	MOV	R4,	R0
cinit_loop:
	LDR	R5,	[R4],	#4  ;read out the variable length in bytes
	TST	R5,	R5
	BEQ	cinit_exit
	LDR	R6,	[R4],	#4  ;read out the variable address
	TST	R6,	#3
	BNE	cinit_bmov
	
cinit_each:
	CMP	R5,	#4
	BLT	cinit_bmov
	LDR	R0,	[R4],	#4
	STR	R0,	[R6],	#4
	SUBS R5,	R5,	#4
	BEQ	cinit_loop
	B	cinit_each

cinit_bmov:
	LDRB	R0,	[R4],	#1
	STRB	R0,	[R6],	#1
	SUBS	R5,	R5,	#1
	BNE	$1
	TST	R4,	#0x3
	BEQ	cinit_loop
	BIC	R4,	R4,	#0x3
	ADD R4,	R4,	#0x4
	B   cinit_loop
$1:
	TST	R6,	#3
	BEQ	cinit_each
	B 	cinit_bmov

cinit_exit:
    nop

    B init_arm_register

IRQ_MASK    .equ  0x80           ; IRQ mask value
FIQ_MASK    .equ  0x40           ; FIQ mask value
MODE_MASK   .equ  0x1F           ; Processor Mode Mask

FIQ_MODE    .equ  0x11           ; Fast Interrupt Mode (FIQ)
IRQ_MODE    .equ  0x12           ; Interrupt Mode (IRQ)
SUP_MODE    .equ  0x13           ; Supervisor Mode
USR_MODE    .equ  0x10           ; User Mode
ABORT_MODE  .equ  0x17           ; Abort Mode
SYS_MODE    .equ  0x1F           ; System mode

STACKSIZE   .equ  0x50

_FIQstack  .usect  ".stack", STACKSIZE
_IRQstack  .usect  ".stack", STACKSIZE
_ABTstack  .usect  ".stack", STACKSIZE
_SVCstack  .usect  ".stack", STACKSIZE

FIQStackAddr  .word _FIQstack 
IRQStackAddr  .word _IRQstack
abtStackAddr  .word _ABTstack
svcStackAddr  .word _SVCstack
c_cinit      .int   cinit

; Initialize arm registers.
init_arm_register:
	MOV	r0, #0
	MOV	r1, #0
	MOV	r2, #0
	MOV	r3, #0
	MOV	r4, #0
	MOV	r5, #0
	MOV	r6, #0
	MOV	r7, #0
	MOV	r8, #0
	MOV	r9, #0
	MOV	r10, #0
	MOV	r11, #0
	MOV	r12, #0



; program entry
	B _c_int00


    .text
    .state32


; SWI handler
INT_SWI:
    LDRH r7, [lr, #-2]
	AND r7, r7, #0xFF

	CMP r7, #0x01
	BEQ DPLL_SWI_service
	B EXIT_SWI

;DPLL SWI service
DPLL_SWI_service:
; enable M latch, N latch, M2 latch and N2 latch
    LDR r0, ADPLL1_REG3_REG_Addr
	LDRH r1, ADPLL1_REG3_REG_Val_1
	LDRH r2, [r0]
	AND r2, r2, r1
	STRH r2, [r0]

    LDR r0, ADPLL1_REG3_REG_Addr
	LDRH r1, ADPLL1_REG3_REG_Val_2
	LDRH r2, [r0]
	ORR r2, r2, r1
	STRH r2, [r0]

    LDR r0, ADPLL1_REG3_REG_Addr
	LDRH r1, ADPLL1_REG3_REG_Val_3
	LDRH r2, [r0]
	AND r2, r2, r1
	STRH r2, [r0]

    LDR r0, ADPLL1_REG3_REG_Addr
	LDRH r1, ADPLL1_REG3_REG_Val_4
	LDRH r2, [r0]
	ORR r2, r2, r1
	STRH r2, [r0]

; soft reset lock sequence initialize

    LDR r0, ADPLL1_REG3_REG_Addr
	LDRH r1, ADPLL1_REG3_REG_Val_5
	LDRH r2, [r0]
	ORR r2, r2, r1
	STRH r2, [r0]

    LDR r0, ADPLL1_REG3_REG_Addr
	LDRH r1, ADPLL1_REG3_REG_Val_6
	LDRH r2, [r0]
	AND r2, r2, r1
	STRH r2, [r0]

    LDR r0, ADPLL1_REG3_REG_Addr
	LDRH r1, ADPLL1_REG3_REG_Val_7
	LDRH r2, [r0]
	ORR r2, r2, r1
	STRH r2, [r0]

    MOV r0, #0xFF
DPLL_wait:
	SUBS r0, r0, #1
	BNE DPLL_wait

    B EXIT_SWI

;DPLL register define
ADPLL1_REG3_REG_Addr   .word  0xFFFECF06
ADPLL1_REG3_REG_Val_1  .word  0x0000BFFF
ADPLL1_REG3_REG_Val_2  .word  0x00004000
ADPLL1_REG3_REG_Val_3  .word  0x0000DFFF
ADPLL1_REG3_REG_Val_4  .word  0x00002000
ADPLL1_REG3_REG_Val_5  .word  0x00000080
ADPLL1_REG3_REG_Val_6  .word  0x0000FF7F
ADPLL1_REG3_REG_Val_7  .word  0x00000080

; exit SWI
EXIT_SWI:
    MOVS pc, lr


	.state16

; DPll SWI
$DPLL_SWI:
    MOV r3, lr
	SWI #0x01
	MOV pc, r3
    
	.sect ".cinit"
    .space 1000
    .end ; Terminate assembly