代码搜索：1Hz
找到约 197 项符合「1Hz」的源代码
代码结果 197
www.eeworm.com/read/173672/9643794
vhd count60.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count60 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/173672/9643804
vhd count24.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count24 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/412366/11202650
vhd divider2.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY divider2 IS
PORT(iCLK:in std_logic;--input,1KHz
oCLK:out std_logic);--output,1Hz
END divider2;
ARCHITECTURE arch OF divider2 IS
SIGNAL
www.eeworm.com/read/412366/11202938
vhd divider2000.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY divider2000 IS
PORT(iCLK:in std_logic;--input,1KHz
oCLK:out std_logic);--output,1Hz
END divider2000;
ARCHITECTURE arch OF divider2000 IS
www.eeworm.com/read/412366/11202957
vhd divider1000.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY divider1000 IS
PORT(iCLK:in std_logic;--input,1KHz
oCLK:out std_logic);--output,1Hz
END divider1000;
ARCHITECTURE arch OF divider1000 IS
www.eeworm.com/read/184494/9099158
txt qiangda1.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count10 is
port( clk:in std_logic; --1hz
en:in std_logic;
clr:in std_logic;
www.eeworm.com/read/166859/9993486
vhd ji.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ji is
port( clk:in std_logic; --1hz
en:in std_logic_vector(3 downto 0);
clr
www.eeworm.com/read/166859/9993937
vhd jiajianfen1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity jiajianfen1 is
port( clk:in std_logic; --1hz
en:in std_logic;
clr:in std_logic
www.eeworm.com/read/422277/10650436
vhd cmp.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity cmp is
port(clk_100:in std_logic; --100HZ输入
clk_1:in std_logic; --1HZ输入
reset:in std_lo
www.eeworm.com/read/422277/10650515
vhd count.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity count is
port(clk_1:in std_logic; --1HZ输入
sw:in std_logic; --状态判断输入
player1,player2:in