jiajianfen1.vhd

来自「VHDL电子抢答器的实现。有多个文件」· VHDL 代码 · 共 38 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity jiajianfen1 is
port( clk:in std_logic; --1hz
en:in std_logic;
clr:in std_logic;
zf,ff:in std_logic;
fen:out std_logic_vector(3 downto 0)
);
end jiajianfen1;

architecture behav of jiajianfen1 is
signal q:integer range 0 to 9;
begin
process(clk,clr)
begin
	if clr='1' then q<=5;
	elsif clk'event and clk='1' then

	if en='1' then

	if zf='1' then 
		if q<9 then q<=q+1;
		else q<=5;end if;
	elsif ff='1' then
		if q>0 then q<=q-1;
		else q<=5;end if;
	end if;
	end if;
	end if;
end process;
fen<=conv_std_logic_vector (q,4);
end behav;