ji.vhd

来自「VHDL电子抢答器的实现。有多个文件」· VHDL 代码 · 共 66 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

 
entity ji is
port( clk:in std_logic; --1hz
en:in std_logic_vector(3 downto 0);
clr:in std_logic;
zf,ff:in std_logic;
fen:out std_logic_vector(3 downto 0)
);

end ji;

 
architecture behav of ji is

SIGNAL B1,B2,B3,B4,q:STD_LOGIC_VECTOR(3 DOWNTO 0);

begin

process(clk,clr)
begin
	if clr='1' then q<="0101";
	elsif clk'event and clk='1' then
   if EN="0001" then
		q<=B1;
   elsif EN="0010" then
		q<=B2;
   elsif EN="0011" then
		q<=B3;
   elsif EN="0100" then
		q<=B4;
   end if;

	if zf='1' then 
		if q<"1001" then q<=q+1;
		else q<="0101";end if;
	elsif ff='1' then
		if q>"0000" then q<=q-1;
		else q<="0101";end if;

	
	end if;
	

 if EN="0001" then
		B1<=q;
   elsif EN="0010" then
		B2<=q;
   elsif EN="0011" then
		B3<=q;
   elsif EN="0100" then
		B4<=q;
   end if;

end if;
end process;
fen<=q;

end behav;