divider2.vhd

以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY divider2 IS
	PORT(iCLK:in std_logic;--input,1KHz
		oCLK:out std_logic);--output,1Hz
END divider2;

ARCHITECTURE arch OF divider2 IS
	SIGNAL counter : integer range 0 to 1023;
BEGIN

	prock:PROCESS(iCLK)
	begin
		if Rising_edge(iCLK) then
			if counter=1023 then
				counter<=0;
			else
				counter<=counter+1;
			end if;
			if counter<=999 then
				oCLK<='1';
			else
				oCLK<='0';
			end if;
		end if;
	end process prock;
	
END arch;