qiangda1.txt

vhdl编写的智力抢答器程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all; 
entity count10 is
port( clk:in std_logic; --1hz
en:in std_logic;
clr:in std_logic;
up,dn:in std_logic;
dout:out std_logic_vector(3 downto 0)
);
end count10; 
architecture behav of count10 is
signal q:integer range 0 to 9;

begin

process(clk,clr)
begin
if clr='1' then q<=3;
elsif clk'event and clk='1' then
if en='1' then
if up='1' then 
if q<9 then q<=q+1;
else q<=3;end if;

elsif dn='1' then
if q>0 then q<=q-1;
else q<=3;end if;
end if;

end if;
end if;
end process;

dout<=conv_std_logic_vector (q,4);
end behav;
--*************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--**************************************************************
ENTITY Debunce is
PORT(
CP : IN STD_LOGIC; -- CLOCK 4MHZ
Key : IN STD_LOGIC; -- Input Signal
DOUT : OUT STD_LOGIC -- Debounce O/P

);
END Debunce;

--**************************************************************
ARCHITECTURE a OF Debunce IS
SIGNAL SAMPLE, DIFF,DLY_OUT: STD_LOGIC; -- Binary 
BEGIN

Free_Counter : Block -- 计数器 & 产生扫描信号 
Signal Q : STD_LOGIC_VECTOR(14 DOWNTO 0);
Signal D0 : STD_LOGIC;
Begin

PROCESS (CP) -- 计数器计数 
Begin
IF CP'Event AND CP='1' then
D0 <= Q(14);
Q <= Q+1; 
END IF;
END PROCESS;

SAMPLE <= Q(14) AND NOT D0; --产生125HZ脉冲? 
END Block Free_Counter; 


Debounce : Block -- Timer Key Debounce
SIGNAL D0, D1, S, R,DLY,NDLY : STD_LOGIC; 
Begin
Process (CP)
Begin
IF CP'EVENT AND CP='1' THEN
IF SAMPLE = '1' THEN
D1 <= D0; D0 <=NOT Key; --二级延迟
S <= D0 AND D1;
R <= NOT D0 AND NOT D1;
END IF; 
END IF;
End Process; 
DLY <= R NOR NDLY; --RS 触发器 
NDLY <=S NOR DLY; 
DLY_OUT <= DLY; --RS 触发器输出