📄 count.vhd
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity count is
port(clk_1:in std_logic; --1HZ输入
sw:in std_logic; --状态判断输入
player1,player2:in std_logic; --选手输入
sum1,sum2:out std_logic_vector(4 downto 0)); --计数输出
end count;
architecture body_count of count is
signal p1,p2:std_logic_vector(4 downto 0); --计数输出
begin
sum1<=p1;
sum2<=p2;
process(player1,player2,sw,clk_1)
begin
if(sw='1') then --处于比赛状态
if(clk_1='0') then
if(player1'event and player1='1') then
p1<=p1+'1';
end if;
if(player2'event and player2='1') then
p2<=p2+'1';
end if;
else
p1<="00000";
p2<="00000";
end if; --比赛状态结束
else p1<="00000";
p2<="00000";
end if;
end process;
end body_count;
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