prev_cmp_uart_txd.fit.qmsg

基于verilog hdl的UART串口发送子程序。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 11 14:34:50 2009 " "Info: Processing started: Mon May 11 14:34:50 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off uart_txd -c uart_txd " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off uart_txd -c uart_txd" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Info: Only one processor detected - disabling parallel compilation" {  } {  } 0 0 "Only one processor detected - disabling parallel compilation" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "uart_txd EP2C5T144C8 " "Info: Selected device EP2C5T144C8 for design \"uart_txd\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5T144I8 " "Info: Device EP2C5T144I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8T144C8 " "Info: Device EP2C8T144C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8T144I8 " "Info: Device EP2C8T144I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS41p/nCEO~ 76 " "Info: Pin ~LVDS41p/nCEO~ is reserved at location 76" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { ~LVDS41p/nCEO~ } } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS41p/nCEO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "13 13 " "Warning: No exact pin location assignment(s) for 13 pins of 13 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk_in " "Info: Pin clk_in not assigned to an exact location on the device" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { clk_in } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 17 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk_out " "Info: Pin clk_out not assigned to an exact location on the device" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { clk_out } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 20 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_out } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "data_in\[0\] " "Info: Pin data_in\[0\] not assigned to an exact location on the device" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { data_in[0] } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "data_in\[1\] " "Info: Pin data_in\[1\] not assigned to an exact location on the device" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { data_in[1] } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "data_in\[2\] " "Info: Pin data_in\[2\] not assigned to an exact location on the device" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { data_in[2] } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "data_in\[3\] " "Info: Pin data_in\[3\] not assigned to an exact location on the device" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { data_in[3] } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "data_in\[4\] " "Info: Pin data_in\[4\] not assigned to an exact location on the device" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { data_in[4] } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "data_in\[5\] " "Info: Pin data_in\[5\] not assigned to an exact location on the device" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { data_in[5] } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "data_in\[6\] " "Info: Pin data_in\[6\] not assigned to an exact location on the device" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { data_in[6] } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "data_in\[7\] " "Info: Pin data_in\[7\] not assigned to an exact location on the device" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { data_in[7] } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "TXD " "Info: Pin TXD not assigned to an exact location on the device" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { TXD } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 21 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { TXD } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "TI " "Info: Pin TI not assigned to an exact location on the device" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { TI } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 22 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { TI } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "txd_en " "Info: Pin txd_en not assigned to an exact location on the device" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { txd_en } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 18 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { txd_en } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1}  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}