uart_txd.hif

基于verilog hdl的UART串口发送子程序。

Version 9.0 Build 132 02/25/2009 SJ Full Version
11
910
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
uart_txd
# storage
db|uart_txd.(0).cnf
db|uart_txd.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_txd.v
3aa63513c4c83a88384706a81caa42f
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
frequency
20000000
PARAMETER_SIGNED_DEC
DEF
baud_rate
9600
PARAMETER_SIGNED_DEC
DEF
sub_freq
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
PARAMETER_SIGNED_BIN
DEF
}
# hierarchies {
|
}
# macro_sequence

# end
# complete