_primary.vhd

来自「基于verilog hdl的UART串口接收子程序。」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity cycloneiii_io_pad is
    generic(
        lpm_type        : string  := "cycloneiii_io_pad"
    );
    port(
        padin           : in     vl_logic;
        padout          : out    vl_logic
    );
end cycloneiii_io_pad;