_primary.vhd

来自「基于verilog hdl的UART串口接收子程序。」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity cycloneii_asmiblock is
    generic(
        lpm_type        : string  := "cycloneii_asmiblock"
    );
    port(
        dclkin          : in     vl_logic;
        scein           : in     vl_logic;
        sdoin           : in     vl_logic;
        data0out        : out    vl_logic;
        oe              : in     vl_logic
    );
end cycloneii_asmiblock;