_primary.vhd

来自「基于verilog hdl的UART串口接收子程序。」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity cycloneiii_ena_reg is
    port(
        clk             : in     vl_logic;
        ena             : in     vl_logic;
        d               : in     vl_logic;
        clrn            : in     vl_logic;
        prn             : in     vl_logic;
        q               : out    vl_logic
    );
end cycloneiii_ena_reg;