_primary.vhd

来自「基于verilog hdl的UART串口接收子程序。」· VHDL 代码 · 共 7 行

library verilog;
use verilog.vl_types.all;
entity CYCLONEIII_PRIM_DFFE is
    -- This module cannot be connected to from
    -- VHDL because it has unnamed ports.
end CYCLONEIII_PRIM_DFFE;