_primary.vhd

来自「基于verilog hdl的UART串口接收子程序。」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity uart_rxd_vlg_sample_tst is
    port(
        RXD             : in     vl_logic;
        clk_in          : in     vl_logic;
        sampler_tx      : out    vl_logic
    );
end uart_rxd_vlg_sample_tst;