uart_rxd.vht

基于verilog hdl的UART串口接收子程序。

BEGIN
	clk_out_expected <= 'X';
WAIT;
END PROCESS t_prcs_clk_out;
-- expected data_out[7]
t_prcs_data_out_7: PROCESS
BEGIN
	data_out_expected(7) <= 'X';
WAIT;
END PROCESS t_prcs_data_out_7;
-- expected data_out[6]
t_prcs_data_out_6: PROCESS
BEGIN
	data_out_expected(6) <= 'X';
WAIT;
END PROCESS t_prcs_data_out_6;
-- expected data_out[5]
t_prcs_data_out_5: PROCESS
BEGIN
	data_out_expected(5) <= 'X';
WAIT;
END PROCESS t_prcs_data_out_5;
-- expected data_out[4]
t_prcs_data_out_4: PROCESS
BEGIN
	data_out_expected(4) <= 'X';
WAIT;
END PROCESS t_prcs_data_out_4;
-- expected data_out[3]
t_prcs_data_out_3: PROCESS
BEGIN
	data_out_expected(3) <= 'X';
WAIT;
END PROCESS t_prcs_data_out_3;
-- expected data_out[2]
t_prcs_data_out_2: PROCESS
BEGIN
	data_out_expected(2) <= 'X';
WAIT;
END PROCESS t_prcs_data_out_2;
-- expected data_out[1]
t_prcs_data_out_1: PROCESS
BEGIN
	data_out_expected(1) <= 'X';
WAIT;
END PROCESS t_prcs_data_out_1;
-- expected data_out[0]
t_prcs_data_out_0: PROCESS
BEGIN
	data_out_expected(0) <= 'X';
WAIT;
END PROCESS t_prcs_data_out_0;

-- Set trigger on real/expected o/ pattern changes                        

t_prcs_trigger_e : PROCESS(RI_expected,clk_out_expected,data_out_expected)
BEGIN
	trigger_e <= NOT trigger_e;
END PROCESS t_prcs_trigger_e;

t_prcs_trigger_r : PROCESS(RI,clk_out,data_out)
BEGIN
	trigger_r <= NOT trigger_r;
END PROCESS t_prcs_trigger_r;


t_prcs_selfcheck : PROCESS
VARIABLE i : INTEGER := 1;
VARIABLE txt : LINE;

VARIABLE last_RI_exp : STD_LOGIC := 'U';
VARIABLE last_clk_out_exp : STD_LOGIC := 'U';
VARIABLE last_data_out_exp : STD_LOGIC_VECTOR(7 DOWNTO 0) := "UUUUUUUU";

VARIABLE on_first_change : trackvec := "111";
BEGIN

WAIT UNTIL (sampler'LAST_VALUE = '1'OR sampler'LAST_VALUE = '0')
	AND sampler'EVENT;
IF (debug_tbench = '1') THEN
	write(txt,string'("Scanning pattern "));
	write(txt,i);
	writeline(output,txt);
	write(txt,string'("| expected "));write(txt,RI_name);write(txt,string'(" = "));write(txt,RI_expected_prev);
	write(txt,string'("| expected "));write(txt,clk_out_name);write(txt,string'(" = "));write(txt,clk_out_expected_prev);
	write(txt,string'("| expected "));write(txt,data_out_name);write(txt,string'(" = "));write(txt,data_out_expected_prev);
	writeline(output,txt);
	write(txt,string'("| real "));write(txt,RI_name);write(txt,string'(" = "));write(txt,RI_prev);
	write(txt,string'("| real "));write(txt,clk_out_name);write(txt,string'(" = "));write(txt,clk_out_prev);
	write(txt,string'("| real "));write(txt,data_out_name);write(txt,string'(" = "));write(txt,data_out_prev);
	writeline(output,txt);
	i := i + 1;
END IF;
IF ( RI_expected_prev /= 'X' ) AND (RI_expected_prev /= 'U' ) AND (RI_prev /= RI_expected_prev) AND (
	(RI_expected_prev /= last_RI_exp) OR
	(on_first_change(1) = '1')
		) THEN
	throw_error("RI",RI_expected_prev,RI_prev);
	num_mismatches(0) <= num_mismatches(0) + 1;
	on_first_change(1) := '0';
	last_RI_exp := RI_expected_prev;
END IF;
IF ( clk_out_expected_prev /= 'X' ) AND (clk_out_expected_prev /= 'U' ) AND (clk_out_prev /= clk_out_expected_prev) AND (
	(clk_out_expected_prev /= last_clk_out_exp) OR
	(on_first_change(2) = '1')
		) THEN
	throw_error("clk_out",clk_out_expected_prev,clk_out_prev);
	num_mismatches(1) <= num_mismatches(1) + 1;
	on_first_change(2) := '0';
	last_clk_out_exp := clk_out_expected_prev;
END IF;
IF ( data_out_expected_prev /= "XXXXXXXX" ) AND (data_out_expected_prev /= "UUUUUUUU" ) AND (data_out_prev /= data_out_expected_prev) AND (
	(data_out_expected_prev /= last_data_out_exp) OR
	(on_first_change(3) = '1')
		) THEN
	throw_error("data_out",data_out_expected_prev,data_out_prev);
	num_mismatches(2) <= num_mismatches(2) + 1;
	on_first_change(3) := '0';
	last_data_out_exp := data_out_expected_prev;
END IF;
    trigger_i <= NOT trigger_i;
END PROCESS t_prcs_selfcheck;


t_prcs_trigger_res : PROCESS(trigger_e,trigger_i,trigger_r)
BEGIN
	trigger <= trigger_i XOR trigger_e XOR trigger_r;
END PROCESS t_prcs_trigger_res;

t_prcs_endsim : PROCESS
VARIABLE txt : LINE;
VARIABLE total_mismatches : INTEGER := 0;
BEGIN
WAIT FOR 1000000 ps;
total_mismatches := num_mismatches(0) + num_mismatches(1) + num_mismatches(2);
IF (total_mismatches = 0) THEN                                              
        write(txt,string'("Simulation passed !"));                        
        writeline(output,txt);                                              
ELSE                                                                        
        write(txt,total_mismatches);                                        
        write(txt,string'(" mismatched vectors : Simulation failed !"));  
        writeline(output,txt);                                              
END IF;                                                                     
WAIT;
END PROCESS t_prcs_endsim;

END ovec_arch;

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

LIBRARY STD;                                                            
USE STD.textio.ALL;                                                     

USE WORK.uart_rxd_vhd_tb_types.ALL;                                         

ENTITY uart_rxd_vhd_vec_tst IS
END uart_rxd_vhd_vec_tst;
ARCHITECTURE uart_rxd_arch OF uart_rxd_vhd_vec_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL RI : STD_LOGIC;
SIGNAL RXD : STD_LOGIC;
SIGNAL clk_in : STD_LOGIC;
SIGNAL clk_out : STD_LOGIC;
SIGNAL data_out : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sampler : sample_type;

COMPONENT uart_rxd
	PORT (
	RI : OUT STD_LOGIC;
	RXD : IN STD_LOGIC;
	clk_in : IN STD_LOGIC;
	clk_out : OUT STD_LOGIC;
	data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END COMPONENT;
COMPONENT uart_rxd_vhd_check_tst
PORT ( 
	RI : IN STD_LOGIC;
	clk_out : IN STD_LOGIC;
	data_out : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	sampler : IN sample_type
);
END COMPONENT;
COMPONENT uart_rxd_vhd_sample_tst
PORT (
	RXD : IN STD_LOGIC;
	clk_in : IN STD_LOGIC;
	sampler : OUT sample_type
	);
END COMPONENT;
BEGIN
	i1 : uart_rxd
	PORT MAP (
-- list connections between master ports and signals
	RI => RI,
	RXD => RXD,
	clk_in => clk_in,
	clk_out => clk_out,
	data_out => data_out
	);

-- RXD
t_prcs_RXD: PROCESS
BEGIN
	RXD <= '0';
WAIT;
END PROCESS t_prcs_RXD;

-- clk_in
t_prcs_clk_in: PROCESS
BEGIN
	clk_in <= '0';
WAIT;
END PROCESS t_prcs_clk_in;
tb_sample : uart_rxd_vhd_sample_tst
PORT MAP (
	RXD => RXD,
	clk_in => clk_in,
	sampler => sampler
	);

tb_out : uart_rxd_vhd_check_tst
PORT MAP (
	RI => RI,
	clk_out => clk_out,
	data_out => data_out,
	sampler => sampler
	);
END uart_rxd_arch;