_primary.vhd

来自「基于verilog hdl的UART串口接收子程序。」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity uart_rxd_vlg_check_tst is
    port(
        RI              : in     vl_logic;
        clk_out         : in     vl_logic;
        data_out        : in     vl_logic_vector(7 downto 0);
        sampler_rx      : in     vl_logic
    );
end uart_rxd_vlg_check_tst;