_primary.vhd

来自「基于verilog hdl的UART串口接收子程序。」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity uart_rxd is
    port(
        clk_in          : in     vl_logic;
        clk_out         : out    vl_logic;
        data_out        : out    vl_logic_vector(7 downto 0);
        RXD             : in     vl_logic;
        RI              : out    vl_logic
    );
end uart_rxd;