adder4.vhd

本设计是设计了一个4位全加器的内容

--***************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--****************************************************

ENTITY ADDER4 IS
  PORT(
       A,B : IN STD_LOGIC_VECTOR(3 downto 0);
       CI  : IN STD_LOGIC;
       SUM : OUT STD_LOGIC_VECTOR(4 downto 0)
      );
END ADDER4;
--***********************************************************
ARCHITECTURE ART OF ADDER4 IS
SIGNAL HALFADD  :  STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
    HALFADD<=('0'&A)+('0'&B);
    SUM<=HALFADD WHEN CI='0' ELSE
         HALFADD+1;
END ART;