📄 pixel_buffer1.v
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module pixel_buffer1(
clk,
rstn,
data_in,
//out_enable,
P6,
P5,
P4
);
input clk,rstn;
input [7:0] data_in;
//input out_enable;
output[7:0] P6;
output[7:0] P5;
output[7:0] P4;
wire [7:0] P6,P5,P4;
reg [7:0] data_reg,data_reg1,data_reg2;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
data_reg <= 8'd0;
data_reg1 <= 8'd0;
data_reg2 <= 8'd0;
end
else
begin
data_reg <= data_in;
data_reg1 <= data_reg;
data_reg2 <= data_reg1;
end
assign P6 = data_reg;
assign P5 = data_reg1;
assign P4 = data_reg2;
endmodule
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