pixel_buffer2.v

来自「采用快速中指滤波算法实现图像的中值滤波」· Verilog 代码 · 共 46 行

module pixel_buffer2(
    clk,
    rstn,
    data_in,
    //out_enable,
    P9,
    P8,
    P7
    );

input         clk,rstn;
input [7:0]   data_in;
//input         out_enable;
output[7:0]   P9;
output[7:0]   P8;
output[7:0]   P7;

wire   [7:0]  P9,P8,P7;

reg   [7:0]   data_reg,data_reg1,data_reg2,data_reg3,data_reg4;

always@(posedge clk or negedge rstn)
  if(!rstn)
    begin
      data_reg  <= 8'd0;
      data_reg1 <= 8'd0;
      data_reg2 <= 8'd0;
      data_reg3 <= 8'd0;
      data_reg4 <= 8'd0;
    end 
  else
    begin
	  data_reg  <= data_in;
	  data_reg1 <= data_reg;
	  data_reg2 <= data_reg1;
	  data_reg3 <= data_reg2;
	  data_reg4 <= data_reg3;
    end

assign P9 = data_reg2;
assign P8 = data_reg3;
assign P7 = data_reg4;



endmodule