enable_generate.v

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/***********************************************************************************
/模块功能：产生输出使能信号enable，enable为高电平时，P1~P9输出有效值，
/                                  enable为低电平时，P1~P9输出高阻态
/时序描述：
/            _   _   _   _   _   _   _   _   _   _   _   _   _   _   _   _   _
/时钟信号clk| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_|
/              __________  _______________ _ _ _ ____________  _______
/P1~P9有效数据   D.C.    \/        有   效      数   据      \/  D.C.
/              __________/\_______________ _ _ _ ____________/\_______
/              ___________________________________________
/ d_in _______|                                           |__________________
/
/                  ___________________________________________
/d_dly ___________|                                           |______________
/
/                      ____________________________________________
/d_dly1 ______________|                                            |_________
/
/                          ____________________________________________
/d_dly2 __________________|                                            |_____
/
/                          ____________________________________
/enable __________________|                                    |_____________
/
/
***********************************************************************************/

module enable_generate(
    clk,
    rstn,
    d_in,
    row_cnt,
    enable
    );

input       d_in;
input [9:0] row_cnt;
input       clk,rstn;
output      enable;

wire    enable;

reg     d_dly,  d_dly1,  d_dly2;
always@(posedge clk)
  begin
    d_dly  <= d_in;
    d_dly1 <= d_dly;
    d_dly2 <= d_dly1;
  end


assign   enable = d_dly & d_dly2 & (row_cnt > 2);

endmodule