pixel_buffer.v

来自「采用快速中指滤波算法实现图像的中值滤波」· Verilog 代码 · 共 43 行

module pixel_buffer(
    clk,
    rstn,
    data_in,
    //out_enable,
    P3,
    P2,
    P1
    );

input         clk,rstn;
input [7:0]   data_in;
//input         out_enable;
output[7:0]   P3;
output[7:0]   P2;
output[7:0]   P1;

wire   [7:0]  P3,P2,P1;

reg   [7:0]   data_reg,data_reg1,data_reg2;

always@(posedge clk or negedge rstn)
  if(!rstn)
    begin
      data_reg <= 8'd0;
      data_reg1 <= 8'd0;
      data_reg2 <= 8'd0;
    end 
  else
    begin
	  data_reg  <= data_in;
	  data_reg1 <= data_reg;
	  data_reg2 <= data_reg1;
    end

assign P3 = data_reg;
assign P2 = data_reg1;
assign P1 = data_reg2;




endmodule