median_filter.v

采用快速中指滤波算法实现图像的中值滤波

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

module median_filter(
	clk,
	data_valuable,
	P1,
	P2,
	P3,
	P4,
	P5,
	P6,
	P7,
	P8,
	P9,
	d_out_valuable,
	median
);

input	clk;
input	data_valuable;
input	[7:0] P1;
input	[7:0] P2;
input	[7:0] P3;
input	[7:0] P4;
input	[7:0] P5;
input	[7:0] P6;
input	[7:0] P7;
input	[7:0] P8;
input	[7:0] P9;
output	d_out_valuable;
output	[7:0] median;

wire	[7:0] SYNTHESIZED_WIRE_0;
wire	[7:0] SYNTHESIZED_WIRE_1;
wire	[7:0] SYNTHESIZED_WIRE_2;
wire	[7:0] SYNTHESIZED_WIRE_3;
wire	[7:0] SYNTHESIZED_WIRE_4;
wire	[7:0] SYNTHESIZED_WIRE_5;
wire	[7:0] SYNTHESIZED_WIRE_6;
wire	[7:0] SYNTHESIZED_WIRE_7;
wire	[7:0] SYNTHESIZED_WIRE_8;
wire	[7:0] SYNTHESIZED_WIRE_9;
wire	[7:0] SYNTHESIZED_WIRE_10;
wire	[7:0] SYNTHESIZED_WIRE_11;
wire	[7:0] SYNTHESIZED_WIRE_12;
wire	[7:0] SYNTHESIZED_WIRE_13;
wire	[7:0] SYNTHESIZED_WIRE_14;
wire	[7:0] SYNTHESIZED_WIRE_15;
wire	[7:0] SYNTHESIZED_WIRE_16;
wire	[7:0] SYNTHESIZED_WIRE_17;
wire	[7:0] SYNTHESIZED_WIRE_18;
wire	[7:0] SYNTHESIZED_WIRE_19;
wire	[7:0] SYNTHESIZED_WIRE_20;
wire	[7:0] SYNTHESIZED_WIRE_21;
wire	[7:0] SYNTHESIZED_WIRE_22;
wire	[7:0] SYNTHESIZED_WIRE_23;
wire	[7:0] SYNTHESIZED_WIRE_24;
wire	[7:0] SYNTHESIZED_WIRE_25;
wire	[7:0] SYNTHESIZED_WIRE_26;
wire	[7:0] SYNTHESIZED_WIRE_27;
wire	[7:0] SYNTHESIZED_WIRE_28;
wire	[7:0] SYNTHESIZED_WIRE_29;
wire	[7:0] SYNTHESIZED_WIRE_30;
wire	[7:0] SYNTHESIZED_WIRE_31;
wire	[7:0] SYNTHESIZED_WIRE_32;
wire	[7:0] SYNTHESIZED_WIRE_33;
wire	[7:0] SYNTHESIZED_WIRE_34;
wire	[7:0] SYNTHESIZED_WIRE_35;
wire	[7:0] SYNTHESIZED_WIRE_36;
wire	[7:0] SYNTHESIZED_WIRE_37;
wire	[7:0] SYNTHESIZED_WIRE_38;
wire	[7:0] SYNTHESIZED_WIRE_39;
wire	SYNTHESIZED_WIRE_40;
wire	SYNTHESIZED_WIRE_41;
wire	SYNTHESIZED_WIRE_42;
wire	SYNTHESIZED_WIRE_43;
wire	SYNTHESIZED_WIRE_44;
wire	SYNTHESIZED_WIRE_45;
wire	SYNTHESIZED_WIRE_46;
wire	SYNTHESIZED_WIRE_47;
wire	[7:0] SYNTHESIZED_WIRE_48;
wire	[7:0] SYNTHESIZED_WIRE_49;
wire	[7:0] SYNTHESIZED_WIRE_50;
wire	[7:0] SYNTHESIZED_WIRE_51;
wire	[7:0] SYNTHESIZED_WIRE_52;
wire	[7:0] SYNTHESIZED_WIRE_53;





compare2num_LH	b2v_c11(.clk(clk),
.data_in1(P3),.data_in2(P2),.high(SYNTHESIZED_WIRE_48),.low(SYNTHESIZED_WIRE_0));

compare2num_LH	b2v_c12(.clk(clk),
.data_in1(P6),.data_in2(P5),.high(SYNTHESIZED_WIRE_49),.low(SYNTHESIZED_WIRE_2));

compare2num_LH	b2v_c13(.clk(clk),
.data_in1(P9),.data_in2(P8),.high(SYNTHESIZED_WIRE_50),.low(SYNTHESIZED_WIRE_4));

compare2num_LH	b2v_c21(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_0),.data_in2(SYNTHESIZED_WIRE_1),.high(SYNTHESIZED_WIRE_7),.low(SYNTHESIZED_WIRE_53));

compare2num_LH	b2v_c22(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_2),.data_in2(SYNTHESIZED_WIRE_3),.high(SYNTHESIZED_WIRE_9),.low(SYNTHESIZED_WIRE_52));

compare2num_LH	b2v_c23(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_4),.data_in2(SYNTHESIZED_WIRE_5),.high(SYNTHESIZED_WIRE_11),.low(SYNTHESIZED_WIRE_51));

compare2num_LH	b2v_c31(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_6),.data_in2(SYNTHESIZED_WIRE_7),.high(SYNTHESIZED_WIRE_34),.low(SYNTHESIZED_WIRE_32));

compare2num_LH	b2v_c32(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_8),.data_in2(SYNTHESIZED_WIRE_9),.high(SYNTHESIZED_WIRE_17),.low(SYNTHESIZED_WIRE_15));

compare2num_LH	b2v_c33(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_10),.data_in2(SYNTHESIZED_WIRE_11),.high(SYNTHESIZED_WIRE_16),.low(SYNTHESIZED_WIRE_14));

compare2num_H	b2v_c41(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_12),.data_in2(SYNTHESIZED_WIRE_13),.high(SYNTHESIZED_WIRE_19));

compare2num_LH	b2v_c42(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_14),.data_in2(SYNTHESIZED_WIRE_15),.high(SYNTHESIZED_WIRE_35),.low(SYNTHESIZED_WIRE_20));

compare2num_L	b2v_c43(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_16),.data_in2(SYNTHESIZED_WIRE_17),.low(SYNTHESIZED_WIRE_22));

compare2num_H	b2v_c51(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_18),.data_in2(SYNTHESIZED_WIRE_19),.high(SYNTHESIZED_WIRE_36));

compare2num_H	b2v_c52(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_20),.data_in2(SYNTHESIZED_WIRE_21),.high(SYNTHESIZED_WIRE_25));

compare2num_L	b2v_c53(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_22),.data_in2(SYNTHESIZED_WIRE_23),.low(SYNTHESIZED_WIRE_38));

compare2num_L	b2v_c61(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_24),.data_in2(SYNTHESIZED_WIRE_25),.low(SYNTHESIZED_WIRE_27));

compare2num_LH	b2v_c71(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_26),.data_in2(SYNTHESIZED_WIRE_27),.high(SYNTHESIZED_WIRE_39),.low(SYNTHESIZED_WIRE_28));

compare2num_H	b2v_c81(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_28),.data_in2(SYNTHESIZED_WIRE_29),.high(SYNTHESIZED_WIRE_31));

compare2num_L	b2v_inst(.clk(clk),
.data_in1(SYNTHESIZED_WIRE_30),.data_in2(SYNTHESIZED_WIRE_31),.low(median));

delay_1T	b2v_inst1(.clk(clk),
.d_in(P7),.d_out(SYNTHESIZED_WIRE_5));

delay_1T	b2v_inst10(.clk(clk),
.d_in(SYNTHESIZED_WIRE_32),.d_out(SYNTHESIZED_WIRE_21));

delay_1T	b2v_inst11(.clk(clk),
.d_in(SYNTHESIZED_WIRE_33),.d_out(SYNTHESIZED_WIRE_18));

delay_1T	b2v_inst12(.clk(clk),
.d_in(SYNTHESIZED_WIRE_34),.d_out(SYNTHESIZED_WIRE_23));

delay_1T	b2v_inst13(.clk(clk),
.d_in(SYNTHESIZED_WIRE_35),.d_out(SYNTHESIZED_WIRE_24));

delay_1T	b2v_inst14(.clk(clk),
.d_in(SYNTHESIZED_WIRE_36),.d_out(SYNTHESIZED_WIRE_37));

delay_1T	b2v_inst15(.clk(clk),
.d_in(SYNTHESIZED_WIRE_37),.d_out(SYNTHESIZED_WIRE_29));

delay_1T	b2v_inst16(.clk(clk),
.d_in(SYNTHESIZED_WIRE_38),.d_out(SYNTHESIZED_WIRE_26));

delay_1T	b2v_inst17(.clk(clk),
.d_in(SYNTHESIZED_WIRE_39),.d_out(SYNTHESIZED_WIRE_30));

data_valuable_delay_1T	b2v_inst19(.d_in(data_valuable),
.clk(clk),.d_out(SYNTHESIZED_WIRE_40));

delay_1T	b2v_inst2(.clk(clk),
.d_in(P4),.d_out(SYNTHESIZED_WIRE_3));

data_valuable_delay_1T	b2v_inst20(.d_in(SYNTHESIZED_WIRE_40),
.clk(clk),.d_out(SYNTHESIZED_WIRE_41));

data_valuable_delay_1T	b2v_inst21(.d_in(SYNTHESIZED_WIRE_41),
.clk(clk),.d_out(SYNTHESIZED_WIRE_42));

data_valuable_delay_1T	b2v_inst22(.d_in(SYNTHESIZED_WIRE_42),
.clk(clk),.d_out(SYNTHESIZED_WIRE_43));

data_valuable_delay_1T	b2v_inst23(.d_in(SYNTHESIZED_WIRE_43),
.clk(clk),.d_out(SYNTHESIZED_WIRE_44));

data_valuable_delay_1T	b2v_inst24(.d_in(SYNTHESIZED_WIRE_44),
.clk(clk),.d_out(SYNTHESIZED_WIRE_45));

data_valuable_delay_1T	b2v_inst25(.d_in(SYNTHESIZED_WIRE_45),
.clk(clk),.d_out(SYNTHESIZED_WIRE_46));

data_valuable_delay_1T	b2v_inst26(.d_in(SYNTHESIZED_WIRE_46),
.clk(clk),.d_out(SYNTHESIZED_WIRE_47));

data_valuable_delay_1T	b2v_inst27(.d_in(SYNTHESIZED_WIRE_47),
.clk(clk),.d_out(d_out_valuable));

delay_1T	b2v_inst3(.clk(clk),
.d_in(P1),.d_out(SYNTHESIZED_WIRE_1));

delay_1T	b2v_inst4(.clk(clk),
.d_in(SYNTHESIZED_WIRE_48),.d_out(SYNTHESIZED_WIRE_6));

delay_1T	b2v_inst5(.clk(clk),
.d_in(SYNTHESIZED_WIRE_49),.d_out(SYNTHESIZED_WIRE_8));

delay_1T	b2v_inst6(.clk(clk),
.d_in(SYNTHESIZED_WIRE_50),.d_out(SYNTHESIZED_WIRE_10));

delay_1T	b2v_inst7(.clk(clk),
.d_in(SYNTHESIZED_WIRE_51),.d_out(SYNTHESIZED_WIRE_33));

delay_1T	b2v_inst8(.clk(clk),
.d_in(SYNTHESIZED_WIRE_52),.d_out(SYNTHESIZED_WIRE_12));

delay_1T	b2v_inst9(.clk(clk),
.d_in(SYNTHESIZED_WIRE_53),.d_out(SYNTHESIZED_WIRE_13));


endmodule