mode3by3_generate.v

采用快速中指滤波算法实现图像的中值滤波

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

module mode3by3_generate(
	clk,
	Rst_n,
	data_valuable,
	data_in,
	d_out_valuable,
	P1,
	P2,
	P3,
	P4,
	P5,
	P6,
	P7,
	P8,
	P9
);

input	clk;
input	Rst_n;
input	data_valuable;
input	[7:0] data_in;
output	d_out_valuable;
output	[7:0] P1;
output	[7:0] P2;
output	[7:0] P3;
output	[7:0] P4;
output	[7:0] P5;
output	[7:0] P6;
output	[7:0] P7;
output	[7:0] P8;
output	[7:0] P9;

wire	[7:0] SYNTHESIZED_WIRE_0;
wire	[7:0] SYNTHESIZED_WIRE_10;
wire	SYNTHESIZED_WIRE_11;
wire	[9:0] SYNTHESIZED_WIRE_3;
wire	SYNTHESIZED_WIRE_5;
wire	SYNTHESIZED_WIRE_7;
wire	SYNTHESIZED_WIRE_8;
wire	[7:0] SYNTHESIZED_WIRE_9;





pixel_buffer	b2v_inst1(.clk(clk),
.rstn(Rst_n),.data_in(SYNTHESIZED_WIRE_0),.P1(P1),.P2(P2),.P3(P3));

line_fifo_control	b2v_inst2(.data_valuable(data_valuable),
.clk(clk),.rstn(Rst_n),.data_in(data_in),.line2_wrreq(SYNTHESIZED_WIRE_7),.line2_rdreq(SYNTHESIZED_WIRE_8),.line1_wrreq(SYNTHESIZED_WIRE_11),.line1_rdreq(SYNTHESIZED_WIRE_5),.data_delay_out(SYNTHESIZED_WIRE_9),.row_cnt(SYNTHESIZED_WIRE_3));

pixel_buffer2	b2v_inst4(.clk(clk),
.rstn(Rst_n),.data_in(data_in),.P7(P7),.P8(P8),.P9(P9));

pixel_buffer1	b2v_inst5(.clk(clk),
.rstn(Rst_n),.data_in(SYNTHESIZED_WIRE_10),.P4(P4),.P5(P5),.P6(P6));

enable_generate	b2v_inst7(.d_in(SYNTHESIZED_WIRE_11),
.clk(clk),.rstn(Rst_n),.row_cnt(SYNTHESIZED_WIRE_3),.enable(d_out_valuable));

line_fifo	b2v_line1(.wrreq(SYNTHESIZED_WIRE_11),
.rdreq(SYNTHESIZED_WIRE_5),.clock(clk),.data(SYNTHESIZED_WIRE_10),.q(SYNTHESIZED_WIRE_0));

line_fifo	b2v_line2(.wrreq(SYNTHESIZED_WIRE_7),
.rdreq(SYNTHESIZED_WIRE_8),.clock(clk),.data(SYNTHESIZED_WIRE_9),.q(SYNTHESIZED_WIRE_10));


endmodule