txsysrtl.v

RTL 异步数据传送模块 用verilog HDL 语言描述 输入为八比特数据

`timescale 1ns / 1ps
module TxSysRTL #(parameter CLKSPERBIT = 18, BITSPERCHAR = 11)
		(input clock, reset, odd_noteven, write,
		input [7:0] Datain,
		output reg Busy,
		output TxData);
		
//RTL States
localparam IDLE = 0, S1 = 1, S2 = 2, S3 = 3;

reg [1:0] TxState;

reg [BITSPERCHAR-1:0] SR;

//Bit timer and bit counter
reg [4:0] BT;
reg [3:0] BC; 

wire parity = odd_noteven ^ (^Datain);

//next state sequential logic
always@(posedge clock or posedge reset)
begin : NState
	if(reset == 1'b1)
		TxState <= IDLE;
	else
		case(TxState)
			IDLE : TxState <= (write)? S1 : IDLE;
			S1 : TxState <= S2;
			S2 : TxState <= (BT == 0)? S3 : S2;
			S3 : TxState <= (BC == 0)? IDLE : S2;
		endcase
end

//RTL operations
always@(posedge clock)
begin : RTL
	case(TxState)
		IDLE : begin
			Busy <= 0;
			SR <= {BITSPERCHAR{1'b1}};
			BC <= BITSPERCHAR;
			BT <= CLKSPERBIT-2;
		end
		S1 : begin
			Busy <= 1;
			SR[9:0] <= {parity ,Datain,1'b0};
		end
		S2 : begin
			BT <= BT-1;
			if (BT == 0) begin 
				BC <= BC-1;
				SR <= {1'b1, SR[BITSPERCHAR-1:1]};
			end
		end
		S3 : if (BC != 0) BT <= CLKSPERBIT-2;
	endcase
end

//serial data output
assign TxData= SR[0];

endmodule