test_txsysrtl.v

来自「RTL 异步数据传送模块 用verilog HDL 语言描述 输入为八比特数」· Verilog 代码 · 共 74 行

`timescale 1ns / 1ps

module test_TXSysRTL_v;

	// Inputs
	reg clock;
	reg reset;
	reg odd_noteven;
	reg write;
	reg [7:0] Datain;

	// Outputs
	wire Busy;
	wire TxData;
	
	//test data array
	reg [7:0] TestData [0:7];
	
	initial begin : load_test_data
		TestData[0] = 8'h53;
		TestData[1] = 8'hAA;
		TestData[2] = 8'hFE;
		TestData[3] = 8'h01;
		TestData[4] = 8'hCB;
		TestData[5] = 8'h78;
		TestData[6] = 8'h96;
		TestData[7] = 8'hD4;
	end

	// Instantiate the Unit Under Test (UUT)
	TxSysRTL uut (
		.clock(clock), 
		.reset(reset), 
		.odd_noteven(odd_noteven), 
		.write(write), 
		.Datain(Datain), 
		.Busy(Busy), 
		.TxData(TxData)
	);
	
	//generate a 32768Hz clock
	initial begin : CLKGEN
		clock = 0;
		forever
			#15259 clock = ~clock;
	end

	initial begin : STIM
		integer test;
		// Initialize Inputs		
		reset = 1;
		odd_noteven = 0;
		write = 0;
		repeat (2) @(negedge clock);
		reset = 0;
		repeat (2) @(negedge clock);
		//transmit test data
		for (test = 0; test <= 7; test = test + 1)
		begin
			Datain = TestData[test];
			write = 1;
			@(negedge clock);
			write = 0;
			@(negedge clock);
			@(negedge Busy); //wait for end of Busy 
			@(negedge clock);
		end
		repeat (5) @(negedge clock);
		$stop;
	end
      
endmodule