distribute_frq.vhd

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity distribute_frq is
port(clk: in  std_logic;
     clk400h: out std_logic;
     clk1Mh: out std_logic
     );
end;

architecture arch of distribute_frq is
signal q1 : integer range 0 to 1249;
signal q3:integer range 0 to 199;
signal y:std_logic:='0';
signal y2:std_logic:='0';
begin
p1:process(clk)  --将1M的时钟2500分频得到400h的信号
begin
if(clk'event and clk='1') then
  if q1=1249 then
     q1<=0;y<=not y;
  else q1<=q1+1;
  end if;
end if;
end process;

p3:process(y) --将400h的信号400分频得到1Mh的信号
begin
if(y'event and y='1') then
  if q3=199 then
     q3<=0;y2<=not y2;
  else
     q3<=q3+1;
  end if;
end if;
end process; 
clk400h<=y;
clk1Mh<=y2;
end;