display.vhd

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity display is
  port (clk400h: in std_logic;
        a:in integer range 0 to 9;
        b:in integer range 0 to 5;
        c:in integer range 0 to 9;
        d:in integer range 0 to 5;
        e:in integer range 0 to 9;
        f:in integer range 0 to 2;
        mux_o :out std_logic_vector(7 downto 0);--数码管显示数组
        sel :out std_logic_vector(5 downto 0)   --数码管选通数组

        );  
end;

architecture arch of display is
signal q:integer range 0 to 5;
signal mux_out:integer range 0 to 9;--数码管输出数组
    
begin
  process (clk400h)
  begin
    if rising_edge(clk400h) then
       if q=5 then q<=0;
       else q<=q+1; 
       end if; 
       case q is       --将需要显示的7个数都转换成mux_out好共用译码程序
         when 0 =>mux_out<= a;sel<="111110";
         when 1 =>mux_out<= b;sel<="111101";
         when 2 =>mux_out<= c;sel<="111011";
         when 3 =>mux_out<= d;sel<="110111";
         when 4 =>mux_out<= e;sel<="101111";--
         when 5 =>mux_out<= f;sel<="011111";

         when others=>null;
       end case;
    end if;
    case mux_out is--实现４位向量与７段数码管输出之间的转换
      when 0=>mux_o<="00111111";
      when 1=>mux_o<="00000110";
      when 2=>mux_o<="01011011";
      when 3=>mux_o<="01001111";
      when 4=>mux_o<="01100110";
      when 5=>mux_o<="01101101";
      when 6=>mux_o<="01111101";
      when 7=>mux_o<="00000111";
      when 8=>mux_o<="01111111";
      when 9=>mux_o<="01101111";
      when others=>mux_o<="01111001";
    end case; 
  end process;
end;