myclock.map.rpt

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选

; distribute_frq.vhd                                          ; yes             ;
; time_form.vhd                                               ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/addcore.inc     ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/look_add.inc    ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/addcore.tdf     ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/look_add.tdf    ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/altshift.tdf    ; yes             ;
+-------------------------------------------------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 128                  ;
; Total registers      ; 95                   ;
; I/O pins             ; 23                   ;
; Shareable expanders  ; 6                    ;
; Parallel expanders   ; 13                   ;
; Maximum fan-out node ; distribute_frq:u1|y2 ;
; Maximum fan-out      ; 53                   ;
; Total fan-out        ; 1083                 ;
; Average fan-out      ; 6.90                 ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sun Dec 30 17:07:11 2007
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off myclock -c myclock
Info: Found 2 design units, including 1 entities, in source file myclock.vhd
    Info: Found design unit 1: myclock-arch
    Info: Found entity 1: myclock
Info: Found 2 design units, including 1 entities, in source file clk_and_modify.vhd
    Info: Found design unit 1: clk_and_modify-arch
    Info: Found entity 1: clk_and_modify
Info: Found 2 design units, including 1 entities, in source file display.vhd
    Info: Found design unit 1: display-arch
    Info: Found entity 1: display
Info: Found 2 design units, including 1 entities, in source file distribute_frq.vhd
    Info: Found design unit 1: distribute_frq-arch
    Info: Found entity 1: distribute_frq
Info: Found 2 design units, including 1 entities, in source file time_form.vhd
    Info: Found design unit 1: time_form-arch
    Info: Found entity 1: time_form
Warning: VHDL Process Statement warning at myclock.vhd(112): signal choose_state_signal is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at myclock.vhd(113): signal sel_signal is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at myclock.vhd(114): signal mux_o_signal is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at myclock.vhd(115): signal mux_o_signal is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at myclock.vhd(117): signal sel_signal is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at myclock.vhd(118): signal mux_o_signal is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at myclock.vhd(119): signal mux_o_signal is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at myclock.vhd(121): OTHERS choice is never selected
Warning: VHDL Signal Declaration warning at distribute_frq.vhd(16): ignored default value for signal y
Warning: VHDL Signal Declaration warning at distribute_frq.vhd(17): ignored default value for signal y2
Info: VHDL Case Statement information at clk_and_modify.vhd(88): OTHERS choice is never selected
Info: VHDL Case Statement information at clk_and_modify.vhd(123): OTHERS choice is never selected
Warning: VHDL Process Statement warning at clk_and_modify.vhd(136): signal sec_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(136): signal sec_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(136): signal min_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(136): signal min_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(136): signal choose is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(137): signal sec_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(137): signal sec_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(137): signal min_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(137): signal min_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(137): signal choose is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal sec_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal sec_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal min_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal min_l_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal min_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal min_h_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal hour_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal hour_l_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal hour_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(139): signal hour_h_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal sec_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal sec_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal min_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal min_l_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal min_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal min_h_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal hour_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal hour_l_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal hour_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(140): signal hour_h_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal sec_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal sec_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal min_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal min_l_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal min_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal min_h_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal hour_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal hour_l_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal hour_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(141): signal hour_h_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal sec_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal sec_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal min_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal min_l_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal min_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal min_h_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal hour_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal hour_l_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal hour_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(142): signal hour_h_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal sec_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal sec_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal min_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal min_l_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal min_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal min_h_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal hour_l is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal hour_l_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal hour_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(143): signal hour_h_alarm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at clk_and_modify.vhd(147): signal choose_state is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at display.vhd(39): OTHERS choice is never selected
Warning: VHDL Process Statement warning at display.vhd(42): signal mux_out is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at display.vhd(53): OTHERS choice is never selected
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 19 buffer(s)
    Info: Ignored 19 SOFT buffer(s)
Info: Duplicate registers merged to single register
    Info: Duplicate register distribute_frq:u1|q3[0] merged to single register display:u4|q[0]
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin clk to global clock signal
    Info: Promoted clock signal driven by pin revert to global clock signal
Info: Implemented 157 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 16 output pins
    Info: Implemented 128 macrocells
    Info: Implemented 6 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 71 warnings
    Info: Processing ended: Sun Dec 30 17:07:22 2007
    Info: Elapsed time: 00:00:10