📄 myclock.tan.qmsg

📁 用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选
💻 QMSG
📖 第 1 页 / 共 5 页
字号:
上一页 1 2 34
{ "Info" "ITDB_TSU_RESULT" "clk_and_modify:u2\|hour_l\[0\] modify_min_hour clk 3.000 ns register " "Info: tsu for register clk_and_modify:u2\|hour_l\[0\] (data pin = modify_min_hour, clock pin = clk) is 3.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.000 ns + Longest pin register " "Info: + Longest pin to register delay is 20.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns modify_min_hour 1 PIN PIN_1 51 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 51; PIN Node = 'modify_min_hour'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { modify_min_hour } "NODE_NAME" } } } { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(8.000 ns) 12.000 ns clk_and_modify:u2\|hour_l\[1\]~1311 2 COMB SEXP22 2 " "Info: 2: + IC(1.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP22; Fanout = 2; COMB Node = 'clk_and_modify:u2\|hour_l\[1\]~1311'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "9.000 ns" { modify_min_hour clk_and_modify:u2|hour_l[1]~1311 } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 18.000 ns clk_and_modify:u2\|hour_l\[0\]~1349 3 COMB LC30 1 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC30; Fanout = 1; COMB Node = 'clk_and_modify:u2\|hour_l\[0\]~1349'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "6.000 ns" { clk_and_modify:u2|hour_l[1]~1311 clk_and_modify:u2|hour_l[0]~1349 } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 19.000 ns clk_and_modify:u2\|hour_l\[0\]~1352 4 COMB LC31 1 " "Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 19.000 ns; Loc. = LC31; Fanout = 1; COMB Node = 'clk_and_modify:u2\|hour_l\[0\]~1352'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "1.000 ns" { clk_and_modify:u2|hour_l[0]~1349 clk_and_modify:u2|hour_l[0]~1352 } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 20.000 ns clk_and_modify:u2\|hour_l\[0\] 5 REG LC32 29 " "Info: 5: + IC(0.000 ns) + CELL(1.000 ns) = 20.000 ns; Loc. = LC32; Fanout = 29; REG Node = 'clk_and_modify:u2\|hour_l\[0\]'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "1.000 ns" { clk_and_modify:u2|hour_l[0]~1352 clk_and_modify:u2|hour_l[0] } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "19.000 ns 95.00 % " "Info: Total cell delay = 19.000 ns ( 95.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 5.00 % " "Info: Total interconnect delay = 1.000 ns ( 5.00 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "20.000 ns" { modify_min_hour clk_and_modify:u2|hour_l[1]~1311 clk_and_modify:u2|hour_l[0]~1349 clk_and_modify:u2|hour_l[0]~1352 clk_and_modify:u2|hour_l[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 21.000 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns distribute_frq:u1\|y 2 REG LC73 22 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC73; Fanout = 22; REG Node = 'distribute_frq:u1\|y'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "1.000 ns" { clk distribute_frq:u1|y } "NODE_NAME" } } } { "D:/xch/myclock/distribute_frq.vhd" "" "" { Text "D:/xch/myclock/distribute_frq.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns distribute_frq:u1\|y2 3 REG LC113 54 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC113; Fanout = 54; REG Node = 'distribute_frq:u1\|y2'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "9.000 ns" { distribute_frq:u1|y distribute_frq:u1|y2 } "NODE_NAME" } } } { "D:/xch/myclock/distribute_frq.vhd" "" "" { Text "D:/xch/myclock/distribute_frq.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 21.000 ns clk_and_modify:u2\|hour_l\[0\] 4 REG LC32 29 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 21.000 ns; Loc. = LC32; Fanout = 29; REG Node = 'clk_and_modify:u2\|hour_l\[0\]'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { distribute_frq:u1|y2 clk_and_modify:u2|hour_l[0] } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.000 ns 80.95 % " "Info: Total cell delay = 17.000 ns ( 80.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 19.05 % " "Info: Total interconnect delay = 4.000 ns ( 19.05 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "21.000 ns" { clk distribute_frq:u1|y distribute_frq:u1|y2 clk_and_modify:u2|hour_l[0] } "NODE_NAME" } } }  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "20.000 ns" { modify_min_hour clk_and_modify:u2|hour_l[1]~1311 clk_and_modify:u2|hour_l[0]~1349 clk_and_modify:u2|hour_l[0]~1352 clk_and_modify:u2|hour_l[0] } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "21.000 ns" { clk distribute_frq:u1|y distribute_frq:u1|y2 clk_and_modify:u2|hour_l[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk alarm clk_and_modify:u2\|sec_l\[0\] 44.000 ns register " "Info: tco from clock clk to destination pin alarm through register clk_and_modify:u2\|sec_l\[0\] is 44.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 21.000 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns distribute_frq:u1\|y 2 REG LC73 22 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC73; Fanout = 22; REG Node = 'distribute_frq:u1\|y'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "1.000 ns" { clk distribute_frq:u1|y } "NODE_NAME" } } } { "D:/xch/myclock/distribute_frq.vhd" "" "" { Text "D:/xch/myclock/distribute_frq.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns distribute_frq:u1\|y2 3 REG LC113 54 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC113; Fanout = 54; REG Node = 'distribute_frq:u1\|y2'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "9.000 ns" { distribute_frq:u1|y distribute_frq:u1|y2 } "NODE_NAME" } } } { "D:/xch/myclock/distribute_frq.vhd" "" "" { Text "D:/xch/myclock/distribute_frq.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 21.000 ns clk_and_modify:u2\|sec_l\[0\] 4 REG LC112 43 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 21.000 ns; Loc. = LC112; Fanout = 43; REG Node = 'clk_and_modify:u2\|sec_l\[0\]'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { distribute_frq:u1|y2 clk_and_modify:u2|sec_l[0] } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.000 ns 80.95 % " "Info: Total cell delay = 17.000 ns ( 80.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 19.05 % " "Info: Total interconnect delay = 4.000 ns ( 19.05 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "21.000 ns" { clk distribute_frq:u1|y distribute_frq:u1|y2 clk_and_modify:u2|sec_l[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.000 ns + Longest register pin " "Info: + Longest register to pin delay is 22.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_and_modify:u2\|sec_l\[0\] 1 REG LC112 43 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC112; Fanout = 43; REG Node = 'clk_and_modify:u2\|sec_l\[0\]'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { clk_and_modify:u2|sec_l[0] } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns clk_and_modify:u2\|alarm~117 2 COMB LC4 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC4; Fanout = 1; COMB Node = 'clk_and_modify:u2\|alarm~117'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "9.000 ns" { clk_and_modify:u2|sec_l[0] clk_and_modify:u2|alarm~117 } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 18.000 ns clk_and_modify:u2\|alarm~124 3 COMB LC11 1 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 18.000 ns; Loc. = LC11; Fanout = 1; COMB Node = 'clk_and_modify:u2\|alarm~124'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "9.000 ns" { clk_and_modify:u2|alarm~117 clk_and_modify:u2|alarm~124 } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 22.000 ns alarm 4 PIN PIN_8 0 " "Info: 4: + IC(0.000 ns) + CELL(4.000 ns) = 22.000 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'alarm'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "4.000 ns" { clk_and_modify:u2|alarm~124 alarm } "NODE_NAME" } } } { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.000 ns 81.82 % " "Info: Total cell delay = 18.000 ns ( 81.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 18.18 % " "Info: Total interconnect delay = 4.000 ns ( 18.18 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "22.000 ns" { clk_and_modify:u2|sec_l[0] clk_and_modify:u2|alarm~117 clk_and_modify:u2|alarm~124 alarm } "NODE_NAME" } } }  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "21.000 ns" { clk distribute_frq:u1|y distribute_frq:u1|y2 clk_and_modify:u2|sec_l[0] } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "22.000 ns" { clk_and_modify:u2|sec_l[0] clk_and_modify:u2|alarm~117 clk_and_modify:u2|alarm~124 alarm } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "choose alarm 24.000 ns Longest " "Info: Longest tpd from source pin choose to destination pin alarm is 24.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns choose 1 PIN PIN_54 70 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 70; PIN Node = 'choose'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { choose } "NODE_NAME" } } } { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns clk_and_modify:u2\|alarm~117 2 COMB LC4 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC4; Fanout = 1; COMB Node = 'clk_and_modify:u2\|alarm~117'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "9.000 ns" { choose clk_and_modify:u2|alarm~117 } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 20.000 ns clk_and_modify:u2\|alarm~124 3 COMB LC11 1 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 20.000 ns; Loc. = LC11; Fanout = 1; COMB Node = 'clk_and_modify:u2\|alarm~124'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "9.000 ns" { clk_and_modify:u2|alarm~117 clk_and_modify:u2|alarm~124 } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 24.000 ns alarm 4 PIN PIN_8 0 " "Info: 4: + IC(0.000 ns) + CELL(4.000 ns) = 24.000 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'alarm'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "4.000 ns" { clk_and_modify:u2|alarm~124 alarm } "NODE_NAME" } } } { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "20.000 ns 83.33 % " "Info: Total cell delay = 20.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 16.67 % " "Info: Total interconnect delay = 4.000 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "24.000 ns" { choose clk_and_modify:u2|alarm~117 clk_and_modify:u2|alarm~124 alarm } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "clk_and_modify:u2\|min_l_alarm\[1\] alarm_modify clk 15.000 ns register " "Info: th for register clk_and_modify:u2\|min_l_alarm\[1\] (data pin = alarm_modify, clock pin = clk) is 15.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 21.000 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1
上一页 1 2 34
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -