myclock.tan.qmsg

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "div_choose_state register clk_and_modify:u2\|choose_state register clk_and_modify:u2\|choose_state 76.92 MHz 13.0 ns Internal " "Info: Clock div_choose_state has Internal fmax of 76.92 MHz between source register clk_and_modify:u2\|choose_state and destination register clk_and_modify:u2\|choose_state (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_and_modify:u2\|choose_state 1 REG LC52 54 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC52; Fanout = 54; REG Node = 'clk_and_modify:u2\|choose_state'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { clk_and_modify:u2|choose_state } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 152 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.000 ns clk_and_modify:u2\|choose_state 2 REG LC52 54 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC52; Fanout = 54; REG Node = 'clk_and_modify:u2\|choose_state'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { clk_and_modify:u2|choose_state clk_and_modify:u2|choose_state } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 152 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 100.00 % " "Info: Total cell delay = 8.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { clk_and_modify:u2|choose_state clk_and_modify:u2|choose_state } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "div_choose_state destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock div_choose_state to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns div_choose_state 1 CLK PIN_84 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_84; Fanout = 1; CLK Node = 'div_choose_state'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { div_choose_state } "NODE_NAME" } } } { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns clk_and_modify:u2\|choose_state 2 REG LC52 54 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC52; Fanout = 54; REG Node = 'clk_and_modify:u2\|choose_state'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "7.000 ns" { div_choose_state clk_and_modify:u2|choose_state } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 152 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "10.000 ns" { div_choose_state clk_and_modify:u2|choose_state } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "div_choose_state source 10.000 ns - Longest register " "Info: - Longest clock path from clock div_choose_state to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns div_choose_state 1 CLK PIN_84 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_84; Fanout = 1; CLK Node = 'div_choose_state'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { div_choose_state } "NODE_NAME" } } } { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns clk_and_modify:u2\|choose_state 2 REG LC52 54 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC52; Fanout = 54; REG Node = 'clk_and_modify:u2\|choose_state'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "7.000 ns" { div_choose_state clk_and_modify:u2|choose_state } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 152 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "10.000 ns" { div_choose_state clk_and_modify:u2|choose_state } "NODE_NAME" } } }  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "10.000 ns" { div_choose_state clk_and_modify:u2|choose_state } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "10.000 ns" { div_choose_state clk_and_modify:u2|choose_state } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 152 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 152 -1 0 } }  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { clk_and_modify:u2|choose_state clk_and_modify:u2|choose_state } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "10.000 ns" { div_choose_state clk_and_modify:u2|choose_state } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "10.000 ns" { div_choose_state clk_and_modify:u2|choose_state } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "revert register time_form:u3\|state register time_form:u3\|state 76.92 MHz 13.0 ns Internal " "Info: Clock revert has Internal fmax of 76.92 MHz between source register time_form:u3\|state and destination register time_form:u3\|state (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns time_form:u3\|state 1 REG LC77 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC77; Fanout = 16; REG Node = 'time_form:u3\|state'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { time_form:u3|state } "NODE_NAME" } } } { "D:/xch/myclock/time_form.vhd" "" "" { Text "D:/xch/myclock/time_form.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.000 ns time_form:u3\|state 2 REG LC77 16 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC77; Fanout = 16; REG Node = 'time_form:u3\|state'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { time_form:u3|state time_form:u3|state } "NODE_NAME" } } } { "D:/xch/myclock/time_form.vhd" "" "" { Text "D:/xch/myclock/time_form.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 100.00 % " "Info: Total cell delay = 8.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { time_form:u3|state time_form:u3|state } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "revert destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock revert to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns revert 1 CLK PIN_2 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_2; Fanout = 1; CLK Node = 'revert'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { revert } "NODE_NAME" } } } { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns time_form:u3\|state 2 REG LC77 16 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC77; Fanout = 16; REG Node = 'time_form:u3\|state'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "0.000 ns" { revert time_form:u3|state } "NODE_NAME" } } } { "D:/xch/myclock/time_form.vhd" "" "" { Text "D:/xch/myclock/time_form.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "3.000 ns" { revert time_form:u3|state } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "revert source 3.000 ns - Longest register " "Info: - Longest clock path from clock revert to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns revert 1 CLK PIN_2 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_2; Fanout = 1; CLK Node = 'revert'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { revert } "NODE_NAME" } } } { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns time_form:u3\|state 2 REG LC77 16 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC77; Fanout = 16; REG Node = 'time_form:u3\|state'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "0.000 ns" { revert time_form:u3|state } "NODE_NAME" } } } { "D:/xch/myclock/time_form.vhd" "" "" { Text "D:/xch/myclock/time_form.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "3.000 ns" { revert time_form:u3|state } "NODE_NAME" } } }  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "3.000 ns" { revert time_form:u3|state } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "3.000 ns" { revert time_form:u3|state } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/xch/myclock/time_form.vhd" "" "" { Text "D:/xch/myclock/time_form.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/xch/myclock/time_form.vhd" "" "" { Text "D:/xch/myclock/time_form.vhd" 38 -1 0 } }  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { time_form:u3|state time_form:u3|state } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "3.000 ns" { revert time_form:u3|state } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "3.000 ns" { revert time_form:u3|state } "NODE_NAME" } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 6 " "Warning: Circuit may not operate. Detected 6 non-operational path(s) clocked by clock clk with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "time_form:u3\|hour_l_12\[3\] display:u4\|mux_out\[3\] clk 4.0 ns " "Info: Found hold time violation between source  pin or register time_form:u3\|hour_l_12\[3\] and destination pin or register display:u4\|mux_out\[3\] for clock clk (Hold time is 4.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "9.000 ns + Largest " "Info: + Largest clock skew is 9.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.000 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns distribute_frq:u1\|y 2 REG LC73 22 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC73; Fanout = 22; REG Node = 'distribute_frq:u1\|y'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "1.000 ns" { clk distribute_frq:u1|y } "NODE_NAME" } } } { "D:/xch/myclock/distribute_frq.vhd" "" "" { Text "D:/xch/myclock/distribute_frq.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns display:u4\|mux_out\[3\] 3 REG LC107 9 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC107; Fanout = 9; REG Node = 'display:u4\|mux_out\[3\]'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { distribute_frq:u1|y display:u4|mux_out[3] } "NODE_NAME" } } } { "D:/xch/myclock/display.vhd" "" "" { Text "D:/xch/myclock/display.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "12.000 ns" { clk distribute_frq:u1|y display:u4|mux_out[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Shortest register " "Info: - Shortest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns time_form:u3\|hour_l_12\[3\] 2 REG LC48 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC48; Fanout = 1; REG Node = 'time_form:u3\|hour_l_12\[3\]'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "0.000 ns" { clk time_form:u3|hour_l_12[3] } "NODE_NAME" } } } { "D:/xch/myclock/time_form.vhd" "" "" { Text "D:/xch/myclock/time_form.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "3.000 ns" { clk time_form:u3|hour_l_12[3] } "NODE_NAME" } } }  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "12.000 ns" { clk distribute_frq:u1|y display:u4|mux_out[3] } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "3.000 ns" { clk time_form:u3|hour_l_12[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns - " "Info: - Micro clock to output delay of source is 1.000 ns" {  } { { "D:/xch/myclock/time_form.vhd" "" "" { Text "D:/xch/myclock/time_form.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns - Shortest register register " "Info: - Shortest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns time_form:u3\|hour_l_12\[3\] 1 REG LC48 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC48; Fanout = 1; REG Node = 'time_form:u3\|hour_l_12\[3\]'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { time_form:u3|hour_l_12[3] } "NODE_NAME" } } } { "D:/xch/myclock/time_form.vhd" "" "" { Text "D:/xch/myclock/time_form.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns display:u4\|mux_out\[3\] 2 REG LC107 9 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC107; Fanout = 9; REG Node = 'display:u4\|mux_out\[3\]'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { time_form:u3|hour_l_12[3] display:u4|mux_out[3] } "NODE_NAME" } } } { "D:/xch/myclock/display.vhd" "" "" { Text "D:/xch/myclock/display.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { time_form:u3|hour_l_12[3] display:u4|mux_out[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "D:/xch/myclock/display.vhd" "" "" { Text "D:/xch/myclock/display.vhd" 27 -1 0 } }  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "12.000 ns" { clk distribute_frq:u1|y display:u4|mux_out[3] } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "3.000 ns" { clk time_form:u3|hour_l_12[3] } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { time_form:u3|hour_l_12[3] display:u4|mux_out[3] } "NODE_NAME" } } }  } 0}