myclock.tan.qmsg

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 7 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "div_choose_state " "Info: Assuming node div_choose_state is an undefined clock" {  } { { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 7 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "div_choose_state" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "revert " "Info: Assuming node revert is an undefined clock" {  } { { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 7 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "revert" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "distribute_frq:u1\|y2 " "Info: Detected ripple clock distribute_frq:u1\|y2 as buffer" {  } { { "D:/xch/myclock/distribute_frq.vhd" "" "" { Text "D:/xch/myclock/distribute_frq.vhd" 31 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "distribute_frq:u1\|y2" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "distribute_frq:u1\|y " "Info: Detected ripple clock distribute_frq:u1\|y as buffer" {  } { { "D:/xch/myclock/distribute_frq.vhd" "" "" { Text "D:/xch/myclock/distribute_frq.vhd" 21 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "distribute_frq:u1\|y" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register clk_and_modify:u2\|hour_one\[1\] register time_form:u3\|hour_h_12\[1\] 32.26 MHz 31.0 ns Internal " "Info: Clock clk has Internal fmax of 32.26 MHz between source register clk_and_modify:u2\|hour_one\[1\] and destination register time_form:u3\|hour_h_12\[1\] (period= 31.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_and_modify:u2\|hour_one\[1\] 1 REG LC34 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC34; Fanout = 12; REG Node = 'clk_and_modify:u2\|hour_one\[1\]'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { clk_and_modify:u2|hour_one[1] } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns time_form:u3\|hour_h_12\[1\] 2 REG LC33 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC33; Fanout = 1; REG Node = 'time_form:u3\|hour_h_12\[1\]'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { clk_and_modify:u2|hour_one[1] time_form:u3|hour_h_12[1] } "NODE_NAME" } } } { "D:/xch/myclock/time_form.vhd" "" "" { Text "D:/xch/myclock/time_form.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { clk_and_modify:u2|hour_one[1] time_form:u3|hour_h_12[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-18.000 ns - Smallest " "Info: - Smallest clock skew is -18.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns time_form:u3\|hour_h_12\[1\] 2 REG LC33 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC33; Fanout = 1; REG Node = 'time_form:u3\|hour_h_12\[1\]'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "0.000 ns" { clk time_form:u3|hour_h_12[1] } "NODE_NAME" } } } { "D:/xch/myclock/time_form.vhd" "" "" { Text "D:/xch/myclock/time_form.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "3.000 ns" { clk time_form:u3|hour_h_12[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 21.000 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/xch/myclock/myclock.vhd" "" "" { Text "D:/xch/myclock/myclock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns distribute_frq:u1\|y 2 REG LC73 22 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC73; Fanout = 22; REG Node = 'distribute_frq:u1\|y'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "1.000 ns" { clk distribute_frq:u1|y } "NODE_NAME" } } } { "D:/xch/myclock/distribute_frq.vhd" "" "" { Text "D:/xch/myclock/distribute_frq.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns distribute_frq:u1\|y2 3 REG LC113 54 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC113; Fanout = 54; REG Node = 'distribute_frq:u1\|y2'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "9.000 ns" { distribute_frq:u1|y distribute_frq:u1|y2 } "NODE_NAME" } } } { "D:/xch/myclock/distribute_frq.vhd" "" "" { Text "D:/xch/myclock/distribute_frq.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 21.000 ns clk_and_modify:u2\|hour_one\[1\] 4 REG LC34 12 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 21.000 ns; Loc. = LC34; Fanout = 12; REG Node = 'clk_and_modify:u2\|hour_one\[1\]'" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { distribute_frq:u1|y2 clk_and_modify:u2|hour_one[1] } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.000 ns 80.95 % " "Info: Total cell delay = 17.000 ns ( 80.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 19.05 % " "Info: Total interconnect delay = 4.000 ns ( 19.05 % )" {  } {  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "21.000 ns" { clk distribute_frq:u1|y distribute_frq:u1|y2 clk_and_modify:u2|hour_one[1] } "NODE_NAME" } } }  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "3.000 ns" { clk time_form:u3|hour_h_12[1] } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "21.000 ns" { clk distribute_frq:u1|y distribute_frq:u1|y2 clk_and_modify:u2|hour_one[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" "" "" { Text "D:/数字电路实验/实验（下）/数字钟/myclock/clk_and_modify.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/xch/myclock/time_form.vhd" "" "" { Text "D:/xch/myclock/time_form.vhd" 11 -1 0 } }  } 0}  } { { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "8.000 ns" { clk_and_modify:u2|hour_one[1] time_form:u3|hour_h_12[1] } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "3.000 ns" { clk time_form:u3|hour_h_12[1] } "NODE_NAME" } } } { "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" "" "" { Report "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock_cmp.qrpt" Compiler "myclock" "UNKNOWN" "V1" "D:/数字电路实验/实验（下）/数字钟/myclock/db/myclock.quartus_db" { Floorplan "" "" "21.000 ns" { clk distribute_frq:u1|y distribute_frq:u1|y2 clk_and_modify:u2|hour_one[1] } "NODE_NAME" } } }  } 0}