📄 myclock.fit.rpt
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; clk_and_modify:u2|hour_ten[1] ; 7 ;
+-----------------------------------+---------+
+-------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+--------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+--------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 200 / 288 ( 69 % ) ;
; PIAs ; 223 / 288 ( 77 % ) ;
+----------------------------+--------------------+
+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 27.88) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 0 ;
; 3 - 5 ; 0 ;
; 6 - 8 ; 0 ;
; 9 - 11 ; 0 ;
; 12 - 14 ; 0 ;
; 15 - 17 ; 0 ;
; 18 - 20 ; 2 ;
; 21 - 23 ; 1 ;
; 24 - 26 ; 0 ;
; 27 - 29 ; 0 ;
; 30 - 32 ; 3 ;
; 33 - 35 ; 2 ;
+-----------------------------------------------+-----------------------------+
+-----------------------------------------------------------------------+
; LAB Macrocells ;
+-----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 16.00) ; Number of LABs (Total = 8) ;
+-----------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 8 ;
+-----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 11 ;
; 2 ; 1 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 0.75) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 7 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC6 ; display:u4|mux_out[1], display:u4|mux_out[0], display:u4|mux_out[2] ; mux_o[1] ;
; A ; LC10 ; clk_and_modify:u2|sec_h[2], clk_and_modify:u2|sec_h[1], clk_and_modify:u2|sec_h[0], clk_and_modify:u2|sec_l[3], clk_and_modify:u2|sec_l[2], clk_and_modify:u2|sec_l[1], clk_and_modify:u2|sec_l[0], clk_and_modify:u2|min_l[0], clk_and_modify:u2|min_l[3], choose, clk_and_modify:u2|choose_state, modify_min_hour, distribute_frq:u1|y2, reset ; clk_and_modify:u2|min_l[0], clk_and_modify:u2|min_l[2], clk_and_modify:u2|min_one[1], clk_and_modify:u2|min_l[3], clk_and_modify:u2|min_h[1], clk_and_modify:u2|min_h[0], clk_and_modify:u2|min_h[2], clk_and_modify:u2|hour_l[1]~1308, clk_and_modify:u2|hour_l[2], clk_and_modify:u2|hour_l[3], clk_and_modify:u2|hour_h[0], clk_and_modify:u2|hour_h[1], clk_and_modify:u2|alarm~117, clk_and_modify:u2|min_l[0]~546, clk_and_modify:u2|min_l[3]~552, clk_and_modify:u2|min_h[0]~532, clk_and_modify:u2|min_h[2]~534, clk_and_modify:u2|hour_l[1]~1341, clk_and_modify:u2|hour_l[0]~1352, clk_and_modify:u2|p1~467sexpbal ;
; A ; LC9 ; clk_and_modify:u2|sec_h[0], clk_and_modify:u2|sec_l[2], clk_and_modify:u2|sec_l[1], clk_and_modify:u2|sec_h[2], choose, clk_and_modify:u2|sec_l[3], clk_and_modify:u2|sec_l[0], distribute_frq:u1|y2, reset ; clk_and_modify:u2|sec_l[0], clk_and_modify:u2|min_l[0], clk_and_modify:u2|sec_h[0], clk_and_modify:u2|min_l[1], clk_and_modify:u2|sec_ten[1], clk_and_modify:u2|min_l[2], clk_and_modify:u2|sec_h[2], clk_and_modify:u2|min_l[3], clk_and_modify:u2|sec_l[3], clk_and_modify:u2|min_h[1], clk_and_modify:u2|min_h[0], clk_and_modify:u2|min_h[2], clk_and_modify:u2|hour_l[1]~1308, clk_and_modify:u2|hour_l[2], clk_and_modify:u2|hour_l[3], clk_and_modify:u2|hour_h[0], clk_and_modify:u2|hour_h[1], clk_and_modify:u2|alarm~124, clk_and_modify:u2|min_l[0]~546, clk_and_modify:u2|min_l[3]~552, clk_and_modify:u2|hour_l[1]~1341, clk_and_modify:u2|hour_l[0]~1352 ;
; A ; LC7 ; clk_and_modify:u2|sec_h[1], choose, clk_and_modify:u2|sec_l[3], clk_and_modify:u2|sec_l[2], clk_and_modify:u2|sec_l[1], clk_and_modify:u2|sec_l[0], clk_and_modify:u2|sec_h[2], distribute_frq:u1|y2, reset ; clk_and_modify:u2|min_l[0], clk_and_modify:u2|min_l[1], clk_and_modify:u2|sec_ten[0], clk_and_modify:u2|sec_h[1], clk_and_modify:u2|min_l[2], clk_and_modify:u2|sec_h[2], clk_and_modify:u2|min_l[3], clk_and_modify:u2|min_h[1], clk_and_modify:u2|min_h[0], clk_and_modify:u2|min_h[2], clk_and_modify:u2|hour_l[1]~1308, clk_and_modify:u2|hour_l[2], clk_and_modify:u2|hour_l[3], clk_and_modify:u2|hour_h[0], clk_and_modify:u2|hour_h[1], clk_and_modify:u2|alarm~124, clk_and_modify:u2|min_l[0]~546, clk_and_modify:u2|min_l[3]~552, clk_and_modify:u2|hour_l[1]~1341, clk_and_modify:u2|hour_l[0]~1352 ;
; A ; LC14 ; clk_and_modify:u2|sec_h[2], clk_and_modify:u2|sec_h[1], clk_and_modify:u2|sec_h[0], clk_and_modify:u2|sec_l[3], clk_and_modify:u2|sec_l[2], clk_and_modify:u2|sec_l[1], clk_and_modify:u2|sec_l[0], clk_and_modify:u2|min_l[0], clk_and_modify:u2|min_l[1], clk_and_modify:u2|min_l[3], choose, clk_and_modify:u2|choose_state, modify_min_hour, distribute_frq:u1|y2, reset ; clk_and_modify:u2|min_l[0], clk_and_modify:u2|min_one[2], clk_and_modify:u2|min_l[3], clk_and_modify:u2|min_h[1], clk_and_modify:u2|min_h[0], clk_and_modify:u2|min_h[2], clk_and_modify:u2|hour_l[1]~1308, clk_and_modify:u2|hour_l[2], clk_and_modify:u2|hour_l[3], clk_and_modify:u2|hour_h[0], clk_and_modify:u2|hour_h[1], clk_and_modify:u2|alarm~117, clk_and_modify:u2|min_l[0]~546, clk_and_modify:u2|min_l[3]~552, clk_and_modify:u2|min_h[0]~532, clk_and_modify:u2|min_h[2]~534, clk_and_modify:u2|hour_l[1]~1341, clk_and_modify:u2|hour_l[0]~1352, clk_and_modify:u2|p1~467sexpbal, clk_and_modify:u2|p1~475sexpbal ;
; A ; LC2 ; clk_and_modify:u2|min_h[2]~534, clk_and_modify:u2|min_h[0], clk_and_modify:u2|min_h[1], clk_and_modify:u2|min_l[3], clk_and_modify:u2|min_l[0], clk_and_modify:u2|min_l[1], clk_and_modify:u2|min_l[2], clk_and_modify:u2|sec_h[2], clk_and_modify:u2|sec_h[1], clk_and_modify:u2|sec_h[0], clk_and_modify:u2|sec_l[3], clk_and_modify:u2|sec_l[2], clk_and_modify:u2|sec_l[1], clk_and_modify:u2|sec_l[0], choose, clk_and_modify:u2|min_h[2], clk_and_modify:u2|choose_state, modify_min_hour, distribute_frq:u1|y2, reset ; clk_and_modify:u2|min_l[0], clk_and_modify:u2|min_l[3], clk_and_modify:u2|min_h[1], clk_and_modify:u2|min_h[0], clk_and_modify:u2|min_h[2], clk_and_modify:u2|hour_l[1]~1308, clk_and_modify:u2|min_ten[2], clk_and_modify:u2|hour_l[2], clk_and_modify:u2|hour_l[3], clk_and_modify:u2|hour_h[0], clk_and_modify:u2|hour_h[1], clk_and_modify:u2|alarm~117, clk_and_modify:u2|min_l[0]~546, clk_and_modify:u2|min_l[3]~552, clk_and_modify:u2|min_h[0]~532, clk_and_modify:u2|min_h[2]~534, clk_and_modify:u2|hour_l[1]~1341, clk_and_modify:u2|hour_l[0]~1352, clk_and_modify:u2|p1~447sexpbal, clk_and_modify:u2|p1~455sexpbal ;
; A ; LC5 ; display:u4|mux_out[0], display:u4|mux_out[1], display:u4|mux_out[2] ; mux_o[2] ;
; A ; LC13 ; clk_and_modify:u2|min_l[0]~546, clk_and_modify:u2|min_h[2], clk_and_modify:u2|min_l[1], clk_and_modify:u2|min_l[2], clk_and_modify:u2|choose_state, modify_min_hour, choose, clk_and_modify:u2|sec_h[2], clk_and_modify:u2|sec_h[1], clk_and_modify:u2|sec_h[0], clk_and_modify:u2|sec_l[3], clk_and_modify:u2|sec_l[2], clk_and_modify:u2|sec_l[1], clk_and_modify:u2|sec_l[0], clk_and_modify:u2|min_h[1], distribute_frq:u1|y2, reset ; clk_and_modify:u2|min_l[1], clk_and_modify:u2|min_one[0], clk_and_modify:u2|min_l[2], clk_and_modify:u2|min_l[3], clk_and_modify:u2|min_h[1], clk_and_modify:u2|min_h[0], clk_and_modify:u2|min_h[2], clk_and_modify:u2|hour_l[1]~1308, clk_and_modify:u2|hour_l[2], clk_and_modify:u2|hour_l[3], clk_and_modify:u2|hour_h[0], clk_and_modify:u2|hour_h[1], clk_and_modify:u2|alarm~117, clk_and_modify:u2|min_l[0]~546, clk_and_modify:u2|min_l[3]~552, clk_and_modify:u2|min_h[0]~532, clk_and_modify:u2|min_h[2]~534, clk_and_modify:u2|hour_l[1]~1341, clk_and_modify:u2|hour_l[0]~1352, clk_and_modify:u2|p1~467sexpbal ;
; A ; LC16 ; clk_and_modify:u2|sec_h[1], clk_and_modify:u2|sec_h[0], clk_and_modify:u2|sec_l[2], clk_and_modify:u2|sec_l[1], choose, clk_and_modify:u2|sec_l[3], clk_and_modify:u2|sec_l[0], clk_and_modify:u2|sec_h[2], distribute_frq:u1|y2, reset
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