myclock.tan.rpt

来自「用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小」· RPT 代码 · 共 316 行 · 第 1/5 页

; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                              ;
+---------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------+--------------------------------+------------------+------------------+--------------+
; Type                            ; Slack                                    ; Required Time ; Actual Time                      ; From                           ; To                             ; From Clock       ; To Clock         ; Failed Paths ;
+---------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------+--------------------------------+------------------+------------------+--------------+
; Worst-case tsu                  ; N/A                                      ; None          ; 3.000 ns                         ; modify_min_hour                ; clk_and_modify:u2|hour_l[0]    ;                  ; clk              ; 0            ;
; Worst-case tco                  ; N/A                                      ; None          ; 44.000 ns                        ; clk_and_modify:u2|hour_l[2]    ; alarm                          ; clk              ;                  ; 0            ;
; Worst-case tpd                  ; N/A                                      ; None          ; 24.000 ns                        ; choose                         ; alarm                          ;                  ;                  ; 0            ;
; Worst-case th                   ; N/A                                      ; None          ; 15.000 ns                        ; choose                         ; clk_and_modify:u2|hour_l[2]    ;                  ; clk              ; 0            ;
; Worst-case Minimum tco          ; N/A                                      ; None          ; 8.000 ns                         ; time_form:u3|am_or_pm          ; am_or_pm                       ; clk              ;                  ; 0            ;
; Worst-case Minimum tpd          ; N/A                                      ; None          ; 24.000 ns                        ; choose                         ; alarm                          ;                  ;                  ; 0            ;
; Clock Setup: 'clk'              ; N/A                                      ; None          ; 32.26 MHz ( period = 31.000 ns ) ; clk_and_modify:u2|hour_one[0]  ; time_form:u3|hour_l_12[0]      ; clk              ; clk              ; 0            ;
; Clock Setup: 'revert'           ; N/A                                      ; None          ; 76.92 MHz ( period = 13.000 ns ) ; time_form:u3|state             ; time_form:u3|state             ; revert           ; revert           ; 0            ;
; Clock Setup: 'div_choose_state' ; N/A                                      ; None          ; 76.92 MHz ( period = 13.000 ns ) ; clk_and_modify:u2|choose_state ; clk_and_modify:u2|choose_state ; div_choose_state ; div_choose_state ; 0            ;
; Clock Hold: 'clk'               ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; time_form:u3|hour_l_12[0]      ; display:u4|mux_out[0]          ; clk              ; clk              ; 6            ;
; Total number of failed paths    ;                                          ;               ;                                  ;                                ;                                ;                  ;                  ; 6            ;
+---------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------+--------------------------------+------------------+------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                ;
+------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name  ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk              ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; div_choose_state ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; revert           ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                      ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------+-----------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                          ; To                          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------+-----------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_one[1] ; time_form:u3|hour_h_12[1]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_one[2] ; time_form:u3|hour_h_12[1]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_one[3] ; time_form:u3|hour_h_12[1]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_ten[0] ; time_form:u3|hour_h_12[1]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_ten[1] ; time_form:u3|hour_h_12[1]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_one[1] ; time_form:u3|hour_h_12[0]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_one[2] ; time_form:u3|hour_h_12[0]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_one[3] ; time_form:u3|hour_h_12[0]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_ten[0] ; time_form:u3|hour_h_12[0]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_ten[1] ; time_form:u3|hour_h_12[0]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_one[1] ; time_form:u3|hour_l_12[2]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_one[2] ; time_form:u3|hour_l_12[2]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_one[3] ; time_form:u3|hour_l_12[2]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_ten[0] ; time_form:u3|hour_l_12[2]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_ten[1] ; time_form:u3|hour_l_12[2]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_one[1] ; time_form:u3|hour_l_12[3]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_one[2] ; time_form:u3|hour_l_12[3]   ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 32.26 MHz ( period = 31.000 ns )                    ; clk_and_modify:u2|hour_one[3] ; time_form:u3|hour_l_12[3]   ; clk        ; clk      ; None                        ; None                      ; None                    ;