fcout.fit.eqn

数字频率计 FPGA 用verilog语言编写

--D1L37Q is counter_24b:inst3|qout[15]~1662 at LC3_B21
--operation mode is normal

D1L37Q = D1_qout[15];


--D1_qout[14] is counter_24b:inst3|qout[14] at LC4_B21
--operation mode is normal

D1_qout[14]_lut_out = D1_qout[14] & (A1L73 & !D1L8 # !A1L33) # !D1_qout[14] & A1L73 & D1L8;
D1_qout[14] = DFFEA(D1_qout[14]_lut_out, E1L1, Reset, , , , );

--D1L17Q is counter_24b:inst3|qout[14]~1663 at LC4_B21
--operation mode is normal

D1L17Q = D1_qout[14];


--D1_qout[13] is counter_24b:inst3|qout[13] at LC5_B21
--operation mode is normal

D1_qout[13]_lut_out = D1_qout[13] & (A1L73 & !D1_qout[12] # !A1L33) # !D1_qout[13] & A1L73 & D1_qout[12];
D1_qout[13] = DFFEA(D1_qout[13]_lut_out, E1L1, Reset, , , , );

--D1L96Q is counter_24b:inst3|qout[13]~1664 at LC5_B21
--operation mode is normal

D1L96Q = D1_qout[13];


--D1_qout[12] is counter_24b:inst3|qout[12] at LC2_B21
--operation mode is normal

D1_qout[12]_lut_out = D1L49 & !D1_qout[12] & !D1L72;
D1_qout[12] = DFFEA(D1_qout[12]_lut_out, E1L1, Reset, , A1L33, , );

--D1L76Q is counter_24b:inst3|qout[12]~1665 at LC2_B21
--operation mode is normal

D1L76Q = D1_qout[12];


--D1_qout[11] is counter_24b:inst3|qout[11] at LC3_B22
--operation mode is normal

D1_qout[11]_lut_out = D1_qout[11] & (A1L83 & !D1L9 # !A1L43) # !D1_qout[11] & A1L83 & D1L9;
D1_qout[11] = DFFEA(D1_qout[11]_lut_out, E1L1, Reset, , , , );

--D1L56Q is counter_24b:inst3|qout[11]~1666 at LC3_B22
--operation mode is normal

D1L56Q = D1_qout[11];


--D1_qout[10] is counter_24b:inst3|qout[10] at LC1_B22
--operation mode is normal

D1_qout[10]_lut_out = D1_qout[10] & (A1L83 & !D1L01 # !A1L43) # !D1_qout[10] & A1L83 & D1L01;
D1_qout[10] = DFFEA(D1_qout[10]_lut_out, E1L1, Reset, , , , );

--D1L36Q is counter_24b:inst3|qout[10]~1667 at LC1_B22
--operation mode is normal

D1L36Q = D1_qout[10];


--D1_qout[9] is counter_24b:inst3|qout[9] at LC2_B22
--operation mode is normal

D1_qout[9]_lut_out = D1_qout[9] & (A1L83 & !D1_qout[8] # !A1L43) # !D1_qout[9] & A1L83 & D1_qout[8];
D1_qout[9] = DFFEA(D1_qout[9]_lut_out, E1L1, Reset, , , , );

--D1L16Q is counter_24b:inst3|qout[9]~1668 at LC2_B22
--operation mode is normal

D1L16Q = D1_qout[9];


--D1_qout[8] is counter_24b:inst3|qout[8] at LC7_B22
--operation mode is normal

D1_qout[8]_lut_out = A1L83 & !D1_qout[8];
D1_qout[8] = DFFEA(D1_qout[8]_lut_out, E1L1, Reset, , A1L43, , );

--D1L95Q is counter_24b:inst3|qout[8]~1669 at LC7_B22
--operation mode is normal

D1L95Q = D1_qout[8];


--D1_qout[7] is counter_24b:inst3|qout[7] at LC6_B13
--operation mode is normal

D1_qout[7]_lut_out = D1_qout[7] & (A1L93 & !D1L11 # !A1L53) # !D1_qout[7] & A1L93 & D1L11;
D1_qout[7] = DFFEA(D1_qout[7]_lut_out, E1L1, Reset, , , , );

--D1L75Q is counter_24b:inst3|qout[7]~1670 at LC6_B13
--operation mode is normal

D1L75Q = D1_qout[7];


--D1_qout[6] is counter_24b:inst3|qout[6] at LC5_B13
--operation mode is normal

D1_qout[6]_lut_out = D1_qout[6] & (A1L93 & !D1L21 # !A1L53) # !D1_qout[6] & A1L93 & D1L21;
D1_qout[6] = DFFEA(D1_qout[6]_lut_out, E1L1, Reset, , , , );

--D1L55Q is counter_24b:inst3|qout[6]~1671 at LC5_B13
--operation mode is normal

D1L55Q = D1_qout[6];


--D1_qout[5] is counter_24b:inst3|qout[5] at LC8_B13
--operation mode is normal

D1_qout[5]_lut_out = D1_qout[5] & (A1L93 & !D1_qout[4] # !A1L53) # !D1_qout[5] & A1L93 & D1_qout[4];
D1_qout[5] = DFFEA(D1_qout[5]_lut_out, E1L1, Reset, , , , );

--D1L35Q is counter_24b:inst3|qout[5]~1672 at LC8_B13
--operation mode is normal

D1L35Q = D1_qout[5];


--D1_qout[4] is counter_24b:inst3|qout[4] at LC7_B13
--operation mode is normal

D1_qout[4]_lut_out = A1L93 & !D1_qout[4];
D1_qout[4] = DFFEA(D1_qout[4]_lut_out, E1L1, Reset, , A1L53, , );

--D1L15Q is counter_24b:inst3|qout[4]~1673 at LC7_B13
--operation mode is normal

D1L15Q = D1_qout[4];


--K1_q[3] is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] at LC5_B16
--operation mode is clrb_cntr

K1_q[3]_lut_out = (K1_q[3] $ K1L7) & D1L59;
K1_q[3] = DFFEA(K1_q[3]_lut_out, E1L1, Reset, , , , );

--K1L71Q is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[3]~0 at LC5_B16
--operation mode is clrb_cntr

K1L71Q = K1_q[3];


--K1_q[2] is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[2] at LC4_B16
--operation mode is clrb_cntr

K1_q[2]_lut_out = (K1_q[2] $ K1L5) & D1L59;
K1_q[2] = DFFEA(K1_q[2]_lut_out, E1L1, Reset, , , , );

--K1L51Q is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[2]~1 at LC4_B16
--operation mode is clrb_cntr

K1L51Q = K1_q[2];

--K1L7 is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT at LC4_B16
--operation mode is clrb_cntr

K1L7 = CARRY(K1_q[2] & (K1L5));


--K1_q[1] is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] at LC3_B16
--operation mode is clrb_cntr

K1_q[1]_lut_out = (K1_q[1] $ K1L3) & D1L59;
K1_q[1] = DFFEA(K1_q[1]_lut_out, E1L1, Reset, , , , );

--K1L31Q is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[1]~2 at LC3_B16
--operation mode is clrb_cntr

K1L31Q = K1_q[1];

--K1L5 is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT at LC3_B16
--operation mode is clrb_cntr

K1L5 = CARRY(K1_q[1] & (K1L3));


--K1_q[0] is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[0] at LC2_B16
--operation mode is clrb_cntr

K1_q[0]_lut_out = (!K1_q[0]) & D1L59;
K1_q[0] = DFFEA(K1_q[0]_lut_out, E1L1, Reset, , , , );

--K1L11Q is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~3 at LC2_B16
--operation mode is clrb_cntr

K1L11Q = K1_q[0];

--K1L3 is counter_24b:inst3|lpm_counter:qout_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT at LC2_B16
--operation mode is clrb_cntr

K1L3 = CARRY(K1_q[0]);


--D1L32 is counter_24b:inst3|always0~153 at LC4_B20
--operation mode is normal

D1L32 = !D1_qout[18] & !D1_qout[17];

--D1L53 is counter_24b:inst3|always0~175 at LC4_B20
--operation mode is normal

D1L53 = !D1_qout[18] & !D1_qout[17];


--D1L301 is counter_24b:inst3|reduce_nor~55 at LC5_B20
--operation mode is normal

D1L301 = D1L33 & D1L32 & D1_qout[19] & D1_qout[16];

--D1L601 is counter_24b:inst3|reduce_nor~59 at LC5_B20
--operation mode is normal

D1L601 = D1L33 & D1L32 & D1_qout[19] & D1_qout[16];


--D1L401 is counter_24b:inst3|reduce_nor~56 at LC8_B20
--operation mode is normal

D1L401 = !D1_qout[22] & !D1_qout[21];

--D1L701 is counter_24b:inst3|reduce_nor~60 at LC8_B20
--operation mode is normal

D1L701 = !D1_qout[22] & !D1_qout[21];


--D1L201 is counter_24b:inst3|reduce_nor~0 at LC6_B20
--operation mode is normal

D1L201 = !D1_qout[20] # !D1_qout[23] # !D1L401 # !D1L301;

--D1L801 is counter_24b:inst3|reduce_nor~61 at LC6_B20
--operation mode is normal

D1L801 = !D1_qout[20] # !D1_qout[23] # !D1L401 # !D1L301;


--D1L42 is counter_24b:inst3|always0~154 at LC7_B20
--operation mode is normal

D1L42 = D1_qout[23] & (D1_qout[22] # D1_qout[21]) # !D1L301;

--D1L63 is counter_24b:inst3|always0~176 at LC7_B20
--operation mode is normal

D1L63 = D1_qout[23] & (D1_qout[22] # D1_qout[21]) # !D1L301;


--D1L58 is counter_24b:inst3|qout[21]~1623 at LC2_B23
--operation mode is normal

D1L58 = D1L201 & !E1L4 & !D1L42;

--D1L78 is counter_24b:inst3|qout[21]~1674 at LC2_B23
--operation mode is normal

D1L78 = D1L201 & !E1L4 & !D1L42;


--D1L3 is counter_24b:inst3|add~356 at LC3_B23
--operation mode is normal

D1L3 = D1_qout[22] & D1_qout[21] & D1_qout[20];

--D1L31 is counter_24b:inst3|add~366 at LC3_B23
--operation mode is normal

D1L31 = D1_qout[22] & D1_qout[21] & D1_qout[20];


--D1L1 is counter_24b:inst3|LessThan~147 at LC7_B16
--operation mode is normal

D1L1 = K1_q[3] & (K1_q[2] # K1_q[1]);

--D1L2 is counter_24b:inst3|LessThan~148 at LC7_B16
--operation mode is normal

D1L2 = K1_q[3] & (K1_q[2] # K1_q[1]);


--D1L52 is counter_24b:inst3|always0~155 at LC3_B20
--operation mode is normal

D1L52 = D1_qout[19] & (D1_qout[18] # D1_qout[17]) # !D1L33;

--D1L73 is counter_24b:inst3|always0~177 at LC3_B20
--operation mode is normal

D1L73 = D1_qout[19] & (D1_qout[18] # D1_qout[17]) # !D1L33;


--D1L62 is counter_24b:inst3|always0~157 at LC6_B18
--operation mode is normal

D1L62 = !D1_qout[10] & !D1_qout[9];

--D1L83 is counter_24b:inst3|always0~178 at LC6_B18
--operation mode is normal

D1L83 = !D1_qout[10] & !D1_qout[9];


--D1L501 is counter_24b:inst3|reduce_nor~57 at LC8_B18
--operation mode is normal

D1L501 = D1L43 & D1L62 & D1_qout[11] & D1_qout[8];

--D1L901 is counter_24b:inst3|reduce_nor~62 at LC8_B18
--operation mode is normal

D1L901 = D1L43 & D1L62 & D1_qout[11] & D1_qout[8];


--D1L72 is counter_24b:inst3|always0~158 at LC3_B18
--operation mode is normal

D1L72 = D1_qout[15] & (D1_qout[14] # D1_qout[13]) # !D1L501;

--D1L93 is counter_24b:inst3|always0~179 at LC3_B18
--operation mode is normal

D1L93 = D1_qout[15] & (D1_qout[14] # D1_qout[13]) # !D1L501;


--D1L82 is counter_24b:inst3|always0~159 at LC4_B18
--operation mode is normal

D1L82 = D1_qout[11] & (D1_qout[10] # D1_qout[9]) # !D1L43;

--D1L04 is counter_24b:inst3|always0~180 at LC4_B18
--operation mode is normal

D1L04 = D1_qout[11] & (D1_qout[10] # D1_qout[9]) # !D1L43;


--D1L92 is counter_24b:inst3|always0~160 at LC6_B16
--operation mode is normal

D1L92 = K1_q[3] & K1_q[0] & !K1_q[2] & !K1_q[1];

--D1L14 is counter_24b:inst3|always0~181 at LC6_B16
--operation mode is normal

D1L14 = K1_q[3] & K1_q[0] & !K1_q[2] & !K1_q[1];


--D1L03 is counter_24b:inst3|always0~161 at LC2_B12
--operation mode is normal

D1L03 = D1_qout[7] & (D1_qout[6] # D1_qout[5]) # !D1L92;

--D1L24 is counter_24b:inst3|always0~182 at LC2_B12
--operation mode is normal

D1L24 = D1_qout[7] & (D1_qout[6] # D1_qout[5]) # !D1L92;


--D1L29 is counter_24b:inst3|qout~1624 at LC7_B18
--operation mode is normal

D1L29 = D1L52 & D1L72 & D1L82 & D1L03;

--D1L79 is counter_24b:inst3|qout~1675 at LC7_B18
--operation mode is normal

D1L79 = D1L52 & D1L72 & D1L82 & D1L03;


--D1L39 is counter_24b:inst3|qout~1625 at LC1_B20
--operation mode is normal

D1L39 = !E1L4 & D1L201 & D1L42;

--D1L89 is counter_24b:inst3|qout~1676 at LC1_B20
--operation mode is normal

D1L89 = !E1L4 & D1L201 & D1L42;


--A1L13 is rtl~3 at LC4_B23
--operation mode is normal

A1L13 = D1L1 & D1L29 # !D1L39;

--A1L04 is rtl~104 at LC4_B23
--operation mode is normal

A1L04 = D1L1 & D1L29 # !D1L39;


--F4_CLK_out is dividers:inst|Half_freq:inst8|CLK_out at LC3_A8
--operation mode is normal

F4_CLK_out_lut_out = !F4_CLK_out;
F4_CLK_out = DFFEA(F4_CLK_out_lut_out, F2_CLK_out, , , , , );

--F4L2Q is dividers:inst|Half_freq:inst8|CLK_out~1 at LC3_A8
--operation mode is normal

F4L2Q = F4_CLK_out;


--E1L1 is mode:inst4|clock_out2~4 at LC4_A8
--operation mode is normal

E1L1 = mode_sel & F4_CLK_out # !mode_sel & (clock_x);

--E1L2 is mode:inst4|clock_out2~5 at LC4_A8
--operation mode is normal

E1L2 = mode_sel & F4_CLK_out # !mode_sel & (clock_x);


--F51_CLK_out is dividers:inst|Half_freq:inst22|CLK_out at LC1_C6
--operation mode is normal

F51_CLK_out_lut_out = !F51_CLK_out;
F51_CLK_out = DFFEA(F51_CLK_out_lut_out, F41_CLK_out, , , , , );

--F51L2Q is dividers:inst|Half_freq:inst22|CLK_out~1 at LC1_C6
--operation mode is normal

F51L2Q = F51_CLK_out;


--F9_CLK_out is dividers:inst|Half_freq:inst14|CLK_out at LC2_C4
--operation mode is normal

F9_CLK_out_lut_out = !F9_CLK_out;
F9_CLK_out = DFFEA(F9_CLK_out_lut_out, F8_CLK_out, , , , , );

--F9L2Q is dividers:inst|Half_freq:inst14|CLK_out~1 at LC2_C4
--operation mode is normal

F9L2Q = F9_CLK_out;


--D1L4 is counter_24b:inst3|add~357 at LC8_B23
--operation mode is normal

D1L4 = D1_qout[21] & D1_qout[20];

--D1L41 is counter_24b:inst3|add~367 at LC8_B23
--operation mode is normal

D1L41 = D1_qout[21] & D1_qout[20];


--A1L63 is rtl~96 at LC3_B24
--operation mode is normal