fcout.sim.qmsg

数字频率计 FPGA 用verilog语言编写

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 06 09:08:45 2007 " "Info: Processing started: Fri Apr 06 09:08:45 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off fcout -c fcout " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off fcout -c fcout" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_LEVEL_VIOLATION" "\|fcout\|dividers:inst\|ten_divider:inst20\|qout\[2\]~reg0 197221390.11 ns high " "Warning: Found clock high time violation at 197221390.11 ns on register \"\|fcout\|dividers:inst\|ten_divider:inst20\|qout\[2\]~reg0\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_LEVEL_VIOLATION" "\|fcout\|dividers:inst\|ten_divider:inst20\|qout\[1\]~reg0 197221390.11 ns high " "Warning: Found clock high time violation at 197221390.11 ns on register \"\|fcout\|dividers:inst\|ten_divider:inst20\|qout\[1\]~reg0\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_LEVEL_VIOLATION" "\|fcout\|dividers:inst\|ten_divider:inst20\|qout\[0\]~reg0 197221390.11 ns high " "Warning: Found clock high time violation at 197221390.11 ns on register \"\|fcout\|dividers:inst\|ten_divider:inst20\|qout\[0\]~reg0\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_LEVEL_VIOLATION" "\|fcout\|dividers:inst\|ten_divider:inst20\|qout\[3\]~reg0 197221390.11 ns high " "Warning: Found clock high time violation at 197221390.11 ns on register \"\|fcout\|dividers:inst\|ten_divider:inst20\|qout\[3\]~reg0\"" {  } {  } 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     40.63 % " "Info: Simulation coverage is      40.63 %" {  } {  } 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "11541732 " "Info: Number of transitions in simulation is 11541732" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 4 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 06 09:22:55 2007 " "Info: Processing ended: Fri Apr 06 09:22:55 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:14:14 " "Info: Elapsed time: 00:14:14" {  } {  } 0}  } {  } 0}