fcout.map.qmsg

数字频率计 FPGA 用verilog语言编写

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 05 22:27:24 2007 " "Info: Processing started: Thu Apr 05 22:27:24 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fcout -c fcout " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fcout -c fcout" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Half_freq.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Half_freq.v" { { "Info" "ISGN_ENTITY_NAME" "1 Half_freq " "Info: Found entity 1: Half_freq" {  } { { "Half_freq.v" "" { Text "D:/fcout/Half_freq.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "ten_divider.v(8) " "Warning: (10268) Verilog HDL information at ten_divider.v(8): Always Construct contains both blocking and non-blocking assignments" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 8 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ten_divider.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ten_divider.v" { { "Info" "ISGN_ENTITY_NAME" "1 ten_divider " "Info: Found entity 1: ten_divider" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter_24b.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file counter_24b.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_24b " "Info: Found entity 1: counter_24b" {  } { { "counter_24b.v" "" { Text "D:/fcout/counter_24b.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "div3.v(8) " "Warning: (10268) Verilog HDL information at div3.v(8): Always Construct contains both blocking and non-blocking assignments" {  } { { "div3.v" "" { Text "D:/fcout/div3.v" 8 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div3.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file div3.v" { { "Info" "ISGN_ENTITY_NAME" "1 div3 " "Info: Found entity 1: div3" {  } { { "div3.v" "" { Text "D:/fcout/div3.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file display.v" { { "Info" "ISGN_ENTITY_NAME" "1 display " "Info: Found entity 1: display" {  } { { "display.v" "" { Text "D:/fcout/display.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mode.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mode.v" { { "Info" "ISGN_ENTITY_NAME" "1 mode " "Info: Found entity 1: mode" {  } { { "mode.v" "" { Text "D:/fcout/mode.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dividers.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dividers.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 dividers " "Info: Found entity 1: dividers" {  } { { "dividers.bdf" "" { Schematic "D:/fcout/dividers.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fcout.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file fcout.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 fcout " "Info: Found entity 1: fcout" {  } { { "fcout.bdf" "" { Schematic "D:/fcout/fcout.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fcout " "Info: Elaborating entity \"fcout\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display display:inst2 " "Info: Elaborating entity \"display\" for hierarchy \"display:inst2\"" {  } { { "fcout.bdf" "inst2" { Schematic "D:/fcout/fcout.bdf" { { 288 816 1032 384 "inst2" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mode mode:inst4 " "Info: Elaborating entity \"mode\" for hierarchy \"mode:inst4\"" {  } { { "fcout.bdf" "inst4" { Schematic "D:/fcout/fcout.bdf" { { 288 472 632 448 "inst4" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 mode.v(10) " "Warning: Verilog HDL assignment warning at mode.v(10): truncated value with size 32 to match size of target (1)" {  } { { "mode.v" "" { Text "D:/fcout/mode.v" 10 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 mode.v(11) " "Warning: Verilog HDL assignment warning at mode.v(11): truncated value with size 32 to match size of target (1)" {  } { { "mode.v" "" { Text "D:/fcout/mode.v" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "clock_hhalf mode.v(31) " "Warning: Verilog HDL Always Construct warning at mode.v(31): variable \"clock_hhalf\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "mode.v" "" { Text "D:/fcout/mode.v" 31 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "clock_hhalf mode.v(33) " "Warning: Verilog HDL Always Construct warning at mode.v(33): variable \"clock_hhalf\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "mode.v" "" { Text "D:/fcout/mode.v" 33 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dividers dividers:inst " "Info: Elaborating entity \"dividers\" for hierarchy \"dividers:inst\"" {  } { { "fcout.bdf" "inst" { Schematic "D:/fcout/fcout.bdf" { { 320 232 376 480 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Half_freq dividers:inst\|Half_freq:inst7 " "Info: Elaborating entity \"Half_freq\" for hierarchy \"dividers:inst\|Half_freq:inst7\"" {  } { { "dividers.bdf" "inst7" { Schematic "D:/fcout/dividers.bdf" { { 760 696 792 888 "inst7" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ten_divider dividers:inst\|ten_divider:inst3 " "Info: Elaborating entity \"ten_divider\" for hierarchy \"dividers:inst\|ten_divider:inst3\"" {  } { { "dividers.bdf" "inst3" { Schematic "D:/fcout/dividers.bdf" { { 112 616 744 208 "inst3" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ten_divider.v(13) " "Warning: Verilog HDL assignment warning at ten_divider.v(13): truncated value with size 32 to match size of target (4)" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ten_divider.v(15) " "Warning: Verilog HDL assignment warning at ten_divider.v(15): truncated value with size 32 to match size of target (4)" {  } { { "ten_divider.v" "" { Text "D:/fcout/ten_divider.v" 15 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div3 dividers:inst\|div3:inst " "Info: Elaborating entity \"div3\" for hierarchy \"dividers:inst\|div3:inst\"" {  } { { "dividers.bdf" "inst" { Schematic "D:/fcout/dividers.bdf" { { 112 48 176 208 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 div3.v(13) " "Warning: Verilog HDL assignment warning at div3.v(13): truncated value with size 32 to match size of target (2)" {  } { { "div3.v" "" { Text "D:/fcout/div3.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 div3.v(14) " "Warning: Verilog HDL assignment warning at div3.v(14): truncated value with size 32 to match size of target (2)" {  } { { "div3.v" "" { Text "D:/fcout/div3.v" 14 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_24b counter_24b:inst3 " "Info: Elaborating entity \"counter_24b\" for hierarchy \"counter_24b:inst3\"" {  } { { "fcout.bdf" "inst3" { Schematic "D:/fcout/fcout.bdf" { { 288 664 792 384 "inst3" "" } } } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "counter_24b:inst3\|qout\[0\]~332 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"counter_24b:inst3\|qout\[0\]~332\"" {  } { { "counter_24b.v" "qout\[0\]~332" { Text "D:/fcout/counter_24b.v" 2 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "169 " "Info: Implemented 169 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "24 " "Info: Implemented 24 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "140 " "Info: Implemented 140 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 05 22:27:30 2007 " "Info: Processing ended: Thu Apr 05 22:27:30 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}