fcout.map.summary

数字频率计 FPGA 用verilog语言编写

Flow Status : Successful - Thu Apr 05 22:27:30 2007
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : fcout
Top-level Entity Name : fcout
Family : FLEX10K
Device : EPF10K10LC84-4
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 140
Total pins : 29
Total memory bits : 0