mode.bsf

数字频率计 FPGA 用verilog语言编写

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 16 16 176 176)
	(text "mode" (rect 5 0 32 12)(font "Arial" ))
	(text "inst" (rect 8 144 25 156)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "s_mode" (rect 0 0 38 12)(font "Arial" ))
		(text "s_mode" (rect 21 27 59 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 1))
	)
	(port
		(pt 0 48)
		(input)
		(text "clock_x" (rect 0 0 37 12)(font "Arial" ))
		(text "clock_x" (rect 21 43 58 55)(font "Arial" ))
		(line (pt 0 48)(pt 16 48)(line_width 1))
	)
	(port
		(pt 0 64)
		(input)
		(text "clock_1k" (rect 0 0 43 12)(font "Arial" ))
		(text "clock_1k" (rect 21 59 64 71)(font "Arial" ))
		(line (pt 0 64)(pt 16 64)(line_width 1))
	)
	(port
		(pt 0 80)
		(input)
		(text "clock_2x" (rect 0 0 43 12)(font "Arial" ))
		(text "clock_2x" (rect 21 75 64 87)(font "Arial" ))
		(line (pt 0 80)(pt 16 80)(line_width 1))
	)
	(port
		(pt 0 96)
		(input)
		(text "clock_5hz" (rect 0 0 48 12)(font "Arial" ))
		(text "clock_5hz" (rect 21 91 69 103)(font "Arial" ))
		(line (pt 0 96)(pt 16 96)(line_width 1))
	)
	(port
		(pt 0 112)
		(input)
		(text "clock_hhalf" (rect 0 0 56 12)(font "Arial" ))
		(text "clock_hhalf" (rect 21 107 77 119)(font "Arial" ))
		(line (pt 0 112)(pt 16 112)(line_width 1))
	)
	(port
		(pt 0 128)
		(input)
		(text "rang_sel" (rect 0 0 41 12)(font "Arial" ))
		(text "rang_sel" (rect 21 123 62 135)(font "Arial" ))
		(line (pt 0 128)(pt 16 128)(line_width 1))
	)
	(port
		(pt 160 32)
		(output)
		(text "clock_out1" (rect 0 0 53 12)(font "Arial" ))
		(text "clock_out1" (rect 86 27 139 39)(font "Arial" ))
		(line (pt 160 32)(pt 144 32)(line_width 1))
	)
	(port
		(pt 160 48)
		(output)
		(text "clock_out2" (rect 0 0 53 12)(font "Arial" ))
		(text "clock_out2" (rect 86 43 139 55)(font "Arial" ))
		(line (pt 160 48)(pt 144 48)(line_width 1))
	)
	(port
		(pt 160 64)
		(output)
		(text "clock_out" (rect 0 0 47 12)(font "Arial" ))
		(text "clock_out" (rect 92 59 139 71)(font "Arial" ))
		(line (pt 160 64)(pt 144 64)(line_width 1))
	)
	(drawing
		(rectangle (rect 16 16 144 144)(line_width 1))
	)
)