fcout.fit.summary

来自「数字频率计 FPGA 用verilog语言编写」· SUMMARY 代码 · 共 12 行

Flow Status : Successful - Thu Apr 05 22:27:46 2007
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : fcout
Top-level Entity Name : fcout
Family : FLEX10K
Device : EPF10K10LC84-4
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 140 / 576 ( 24 % )
Total pins : 29 / 59 ( 49 % )
Total memory bits : 0 / 6,144 ( 0 % )