mode.v

数字频率计 FPGA 用verilog语言编写

module mode(s_mode,rang_sel,clock_x,clock_1k,clock_2x,clock_hhalf,clock_5hz,clock_out1,clock_out2,clock_out);
input s_mode,clock_x,clock_1k,clock_2x,clock_5hz,clock_hhalf,rang_sel;
output clock_out1,clock_out2,clock_out;
reg clock_out1;
reg clock_out2;
reg clock_out;
reg D=1'b0;
always@(s_mode)
	begin
	    if(s_mode==1)  begin D<=1;  end
	    else  begin D<=0; end
	end
always@(D or clock_2x or clock_x  or clock_1k or clock_5hz or rang_sel )
	begin
   		if(D==1)    //低频测周
			begin
	  	clock_out1<=clock_2x;  
	  	clock_out2<=clock_1k;
	    clock_out<=clock_2x;
			end
   		else       //高频直接测频
   			begin
              if(rang_sel==0) 
					begin
   	 	 		clock_out1<=clock_5hz;
	 			clock_out2<=clock_x;
	     		clock_out<=clock_5hz;
					end
			  else 
					begin
				clock_out1<=clock_hhalf;
	 			clock_out2<=clock_x;
	     		clock_out<=clock_hhalf;
				    end
  		    end
	end
endmodule