myf_adder.vhd

用例化语句和case语句编写的全加器的VHDL描述。

library ieee;
use ieee.std_logic_1164.all;
entity myf_adder is
	port(ain,bin,cin:in std_logic;
		cout,sum:out std_logic);
end myf_adder;
architecture bhv of myf_adder is
	component myh_adder
		port(a,b:in std_logic;
		     co,so:out std_logic);
	end component;
		component myor2a
		   port(a,b:in std_logic;
	           c:out std_logic);
		end component;
signal d,e,f:std_logic;
begin
u1:myh_adder port map(a=>ain,b=>bin,co=>d,so=>e);
u2:myh_adder port map(a=>e,b=>cin,co=>f,so=>sum);
u3:   myor2a port map(a=>d,b=>f,c=>cout);
end bhv;

library ieee;
use ieee.std_logic_1164.all;
entity myh_adder is
	port(a,b:in std_logic;
	        co,so:out std_logic);
end myh_adder;
architecture fh1 of myh_adder is
begin
     process(a,b)
     begin
       if a='1' and b='1' then
         co<='1';
         so<='0';
        elsif a='1' and b='0' then
          co<='0';
           so<='1';
           elsif a='0' and b='1' then
               co<='0';
               so<='1';
              elsif a='0' and b='0' then
                  co<='0';
                   so<='0';
        end if;
      end process;
end fh1;

library ieee;
use ieee.std_logic_1164.all;
entity myor2a is
	port(a,b:in std_logic;
	        c:out std_logic);
end myor2a;
architecture one of myor2a is
begin
 c<=a or b;
end one;